1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Bluewater Systems Snapper 9260/9G20 modules
4  *
5  * (C) Copyright 2011 Bluewater Systems
6  *   Author: Andre Renaud <andre@bluewatersys.com>
7  *   Author: Ryan Mallon <ryan@bluewatersys.com>
8  */
9 
10 #include <common.h>
11 #include <atmel_lcd.h>
12 #include <atmel_lcdc.h>
13 #include <atmel_mci.h>
14 #include <dm.h>
15 #include <lcd.h>
16 #include <net.h>
17 #ifndef CONFIG_DM_ETH
18 #include <netdev.h>
19 #endif
20 #include <asm/gpio.h>
21 #include <asm/io.h>
22 #include <asm/mach-types.h>
23 #include <asm/arch/at91sam9g45_matrix.h>
24 #include <asm/arch/at91sam9_smc.h>
25 #include <asm/arch/at91_common.h>
26 #include <asm/arch/at91_emac.h>
27 #include <asm/arch/at91_rstc.h>
28 #include <asm/arch/at91_rtc.h>
29 #include <asm/arch/at91_sck.h>
30 #include <asm/arch/atmel_serial.h>
31 #include <asm/arch/clk.h>
32 #include <asm/arch/gpio.h>
33 #include <dm/uclass-internal.h>
34 
35 #ifdef CONFIG_GURNARD_SPLASH
36 #include "splash_logo.h"
37 #endif
38 
39 DECLARE_GLOBAL_DATA_PTR;
40 
41 /* IO Expander pins */
42 #define IO_EXP_ETH_RESET	(0 << 1)
43 #define IO_EXP_ETH_POWER	(1 << 1)
44 
45 #ifdef CONFIG_MACB
46 static void gurnard_macb_hw_init(void)
47 {
48 	struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
49 
50 	at91_periph_clk_enable(ATMEL_ID_EMAC);
51 
52 	/*
53 	 * Enable pull-up on:
54 	 *	RXDV (PA12) => MODE0 - PHY also has pull-up
55 	 *	ERX0 (PA13) => MODE1 - PHY also has pull-up
56 	 *	ERX1 (PA15) => MODE2 - PHY also has pull-up
57 	 */
58 	writel(pin_to_mask(AT91_PIN_PA15) |
59 	       pin_to_mask(AT91_PIN_PA12) |
60 	       pin_to_mask(AT91_PIN_PA13),
61 	       &pioa->puer);
62 
63 	at91_phy_reset();
64 
65 	at91_macb_hw_init();
66 }
67 #endif
68 
69 #ifdef CONFIG_CMD_NAND
70 static int gurnard_nand_hw_init(void)
71 {
72 	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
73 	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
74 	ulong flags;
75 	int ret;
76 
77 	/* Enable CS3 as NAND/SmartMedia */
78 	setbits_le32(&matrix->ebicsa, AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
79 
80 	/* Configure SMC CS3 for NAND/SmartMedia */
81 	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
82 	       AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
83 	       &smc->cs[3].setup);
84 	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
85 	       AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
86 	       &smc->cs[3].pulse);
87 	writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
88 	       &smc->cs[3].cycle);
89 #ifdef CONFIG_SYS_NAND_DBW_16
90 	flags = AT91_SMC_MODE_DBW_16;
91 #else
92 	flags = AT91_SMC_MODE_DBW_8;
93 #endif
94 	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
95 	       AT91_SMC_MODE_EXNW_DISABLE |
96 	       flags |
97 	       AT91_SMC_MODE_TDF_CYCLE(3),
98 	       &smc->cs[3].mode);
99 
100 	ret = gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand_rdy");
101 	if (ret)
102 		return ret;
103 	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
104 
105 	/* Enable NandFlash */
106 	ret = gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand_ce");
107 	if (ret)
108 		return ret;
109 	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
110 
111 	return 0;
112 }
113 #endif
114 
115 #ifdef CONFIG_GURNARD_SPLASH
116 static void lcd_splash(int width, int height)
117 {
118 	u16 colour;
119 	int x, y;
120 	u16 *base_addr = (u16 *)gd->video_bottom;
121 
122 	memset(base_addr, 0xff, width * height * 2);
123 	/*
124 	 * Blit the logo to the center of the screen
125 	 */
126 	for (y = 0; y < BMP_LOGO_HEIGHT; y++) {
127 		for (x = 0; x < BMP_LOGO_WIDTH; x++) {
128 			int posx, posy;
129 			colour = bmp_logo_palette[bmp_logo_bitmap[
130 			    y * BMP_LOGO_WIDTH + x]];
131 			posx = x + (width - BMP_LOGO_WIDTH) / 2;
132 			posy = y;
133 			base_addr[posy * width + posx] = colour;
134 		}
135 	}
136 }
137 #endif
138 
139 #ifdef CONFIG_DM_VIDEO
140 static void at91sam9g45_lcd_hw_init(void)
141 {
142 	at91_set_A_periph(AT91_PIN_PE0, 0);	/* LCDDPWR */
143 	at91_set_A_periph(AT91_PIN_PE2, 0);	/* LCDCC */
144 	at91_set_A_periph(AT91_PIN_PE3, 0);	/* LCDVSYNC */
145 	at91_set_A_periph(AT91_PIN_PE4, 0);	/* LCDHSYNC */
146 	at91_set_A_periph(AT91_PIN_PE5, 0);	/* LCDDOTCK */
147 
148 	at91_set_A_periph(AT91_PIN_PE7, 0);	/* LCDD0 */
149 	at91_set_A_periph(AT91_PIN_PE8, 0);	/* LCDD1 */
150 	at91_set_A_periph(AT91_PIN_PE9, 0);	/* LCDD2 */
151 	at91_set_A_periph(AT91_PIN_PE10, 0);	/* LCDD3 */
152 	at91_set_A_periph(AT91_PIN_PE11, 0);	/* LCDD4 */
153 	at91_set_A_periph(AT91_PIN_PE12, 0);	/* LCDD5 */
154 	at91_set_A_periph(AT91_PIN_PE13, 0);	/* LCDD6 */
155 	at91_set_A_periph(AT91_PIN_PE14, 0);	/* LCDD7 */
156 	at91_set_A_periph(AT91_PIN_PE15, 0);	/* LCDD8 */
157 	at91_set_A_periph(AT91_PIN_PE16, 0);	/* LCDD9 */
158 	at91_set_A_periph(AT91_PIN_PE17, 0);	/* LCDD10 */
159 	at91_set_A_periph(AT91_PIN_PE18, 0);	/* LCDD11 */
160 	at91_set_A_periph(AT91_PIN_PE19, 0);	/* LCDD12 */
161 	at91_set_B_periph(AT91_PIN_PE20, 0);	/* LCDD13 */
162 	at91_set_A_periph(AT91_PIN_PE21, 0);	/* LCDD14 */
163 	at91_set_A_periph(AT91_PIN_PE22, 0);	/* LCDD15 */
164 	at91_set_A_periph(AT91_PIN_PE23, 0);	/* LCDD16 */
165 	at91_set_A_periph(AT91_PIN_PE24, 0);	/* LCDD17 */
166 	at91_set_A_periph(AT91_PIN_PE25, 0);	/* LCDD18 */
167 	at91_set_A_periph(AT91_PIN_PE26, 0);	/* LCDD19 */
168 	at91_set_A_periph(AT91_PIN_PE27, 0);	/* LCDD20 */
169 	at91_set_B_periph(AT91_PIN_PE28, 0);	/* LCDD21 */
170 	at91_set_A_periph(AT91_PIN_PE29, 0);	/* LCDD22 */
171 	at91_set_A_periph(AT91_PIN_PE30, 0);	/* LCDD23 */
172 
173 	at91_periph_clk_enable(ATMEL_ID_LCDC);
174 }
175 #endif
176 
177 #ifdef CONFIG_GURNARD_FPGA
178 /**
179  * Initialise the memory bus settings so that we can talk to the
180  * memory mapped FPGA
181  */
182 static int fpga_hw_init(void)
183 {
184 	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
185 	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
186 	int i;
187 
188 	setbits_le32(&matrix->ebicsa, AT91_MATRIX_EBI_CS1A_SDRAMC);
189 
190 	at91_set_a_periph(2, 4, 0); /* EBIA21 */
191 	at91_set_a_periph(2, 5, 0); /* EBIA22 */
192 	at91_set_a_periph(2, 6, 0); /* EBIA23 */
193 	at91_set_a_periph(2, 7, 0); /* EBIA24 */
194 	at91_set_a_periph(2, 12, 0); /* EBIA25 */
195 	for (i = 15; i <= 31; i++) /* EBINWAIT & EBID16 - 31 */
196 		at91_set_a_periph(2, i, 0);
197 
198 	/* configure SMC cs0 for FPGA access timing */
199 	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(2) |
200 	       AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(2),
201 	       &smc->cs[0].setup);
202 	writel(AT91_SMC_PULSE_NWE(5) | AT91_SMC_PULSE_NCS_WR(4) |
203 	       AT91_SMC_PULSE_NRD(6) | AT91_SMC_PULSE_NCS_RD(4),
204 	       &smc->cs[0].pulse);
205 	writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
206 	       &smc->cs[0].cycle);
207 	writel(AT91_SMC_MODE_BAT |
208 	       AT91_SMC_MODE_EXNW_DISABLE |
209 	       AT91_SMC_MODE_DBW_32 |
210 	       AT91_SMC_MODE_TDF |
211 	       AT91_SMC_MODE_TDF_CYCLE(2),
212 	       &smc->cs[0].mode);
213 
214 	/* Do a write to within EBI_CS1 to enable the SDCK */
215 	writel(0, ATMEL_BASE_CS1);
216 
217 	return 0;
218 }
219 #endif
220 
221 #ifdef CONFIG_CMD_USB
222 
223 #define USB0_ENABLE_PIN		AT91_PIN_PB22
224 #define USB1_ENABLE_PIN		AT91_PIN_PB23
225 
226 void gurnard_usb_init(void)
227 {
228 	at91_set_gpio_output(USB0_ENABLE_PIN, 1);
229 	at91_set_gpio_value(USB0_ENABLE_PIN, 0);
230 	at91_set_gpio_output(USB1_ENABLE_PIN, 1);
231 	at91_set_gpio_value(USB1_ENABLE_PIN, 0);
232 }
233 #endif
234 
235 #ifdef CONFIG_GENERIC_ATMEL_MCI
236 int cpu_mmc_init(bd_t *bis)
237 {
238 	return atmel_mci_init((void *)ATMEL_BASE_MCI0);
239 }
240 #endif
241 
242 static void gurnard_enable_console(int enable)
243 {
244 	at91_set_gpio_output(AT91_PIN_PB14, 1);
245 	at91_set_gpio_value(AT91_PIN_PB14, enable ? 0 : 1);
246 }
247 
248 void at91sam9g45_slowclock_init(void)
249 {
250 	/*
251 	 * On AT91SAM9G45 revC CPUs, the slow clock can be based on an
252 	 * internal impreciseRC oscillator or an external 32kHz oscillator.
253 	 * Switch to the latter.
254 	 */
255 	unsigned i, tmp;
256 	ulong *reg = (ulong *)ATMEL_BASE_SCKCR;
257 
258 	tmp = readl(reg);
259 	if ((tmp & AT91SAM9G45_SCKCR_OSCSEL) == AT91SAM9G45_SCKCR_OSCSEL_RC) {
260 		timer_init();
261 		tmp |= AT91SAM9G45_SCKCR_OSC32EN;
262 		writel(tmp, reg);
263 		for (i = 0; i < 1200; i++)
264 			udelay(1000);
265 		tmp |= AT91SAM9G45_SCKCR_OSCSEL_32;
266 		writel(tmp, reg);
267 		udelay(200);
268 		tmp &= ~AT91SAM9G45_SCKCR_RCEN;
269 		writel(tmp, reg);
270 	}
271 }
272 
273 int board_early_init_f(void)
274 {
275 	at91_seriald_hw_init();
276 	gurnard_enable_console(1);
277 
278 	return 0;
279 }
280 
281 int board_init(void)
282 {
283 	const char *rev_str;
284 #ifdef CONFIG_CMD_NAND
285 	int ret;
286 #endif
287 
288 	at91_periph_clk_enable(ATMEL_ID_PIOA);
289 	at91_periph_clk_enable(ATMEL_ID_PIOB);
290 	at91_periph_clk_enable(ATMEL_ID_PIOC);
291 	at91_periph_clk_enable(ATMEL_ID_PIODE);
292 
293 	at91sam9g45_slowclock_init();
294 
295 	/*
296 	 * Clear the RTC IDR to disable all IRQs. Avoid issues when Linux
297 	 * boots with spurious IRQs.
298 	 */
299 	writel(0xffffffff, AT91_RTC_IDR);
300 
301 	/* Make sure that the reset signal is attached properly */
302 	setbits_le32(AT91_ASM_RSTC_MR, AT91_RSTC_KEY | AT91_RSTC_MR_URSTEN);
303 
304 	gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260;
305 
306 	/* Address of boot parameters */
307 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
308 
309 #ifdef CONFIG_CMD_NAND
310 	ret = gurnard_nand_hw_init();
311 	if (ret)
312 		return ret;
313 #endif
314 #ifdef CONFIG_ATMEL_SPI
315 	at91_spi0_hw_init(1 << 4);
316 #endif
317 
318 #ifdef CONFIG_MACB
319 	gurnard_macb_hw_init();
320 #endif
321 
322 #ifdef CONFIG_GURNARD_FPGA
323 	fpga_hw_init();
324 #endif
325 
326 #ifdef CONFIG_CMD_USB
327 	gurnard_usb_init();
328 #endif
329 
330 #ifdef CONFIG_CMD_MMC
331 	at91_set_A_periph(AT91_PIN_PA12, 0);
332 	at91_set_gpio_output(AT91_PIN_PA8, 1);
333 	at91_set_gpio_value(AT91_PIN_PA8, 0);
334 	at91_mci_hw_init();
335 #endif
336 
337 #ifdef CONFIG_DM_VIDEO
338 	at91sam9g45_lcd_hw_init();
339 	at91_set_A_periph(AT91_PIN_PE6, 1);	/* power up */
340 
341 	/* Select the second timing index for board rev 2 */
342 	rev_str = env_get("board_rev");
343 	if (rev_str && !strncmp(rev_str, "2", 1)) {
344 		struct udevice *dev;
345 
346 		uclass_find_first_device(UCLASS_VIDEO, &dev);
347 		if (dev) {
348 			struct atmel_lcd_platdata *plat = dev_get_platdata(dev);
349 
350 			plat->timing_index = 1;
351 		}
352 	}
353 #endif
354 
355 	return 0;
356 }
357 
358 int board_late_init(void)
359 {
360 	u_int8_t env_enetaddr[8];
361 	char *env_str;
362 	char *end;
363 	int i;
364 
365 	/*
366 	 * Set MAC address so we do not need to init Ethernet before Linux
367 	 * boot
368 	 */
369 	env_str = env_get("ethaddr");
370 	if (env_str) {
371 		struct at91_emac *emac = (struct at91_emac *)ATMEL_BASE_EMAC;
372 		/* Parse MAC address */
373 		for (i = 0; i < 6; i++) {
374 			env_enetaddr[i] = env_str ?
375 				simple_strtoul(env_str, &end, 16) : 0;
376 			if (env_str)
377 				env_str = (*end) ? end+1 : end;
378 		}
379 
380 		/* Set hardware address */
381 		writel(env_enetaddr[0] | env_enetaddr[1] << 8 |
382 		       env_enetaddr[2] << 16 | env_enetaddr[3] << 24,
383 		       &emac->sa2l);
384 		writel((env_enetaddr[4] | env_enetaddr[5] << 8), &emac->sa2h);
385 
386 		printf("MAC:   %s\n", env_get("ethaddr"));
387 	} else {
388 		/* Not set in environment */
389 		printf("MAC:   not set\n");
390 	}
391 #ifdef CONFIG_GURNARD_SPLASH
392 	lcd_splash(480, 272);
393 #endif
394 
395 	return 0;
396 }
397 
398 #ifndef CONFIG_DM_ETH
399 int board_eth_init(bd_t *bis)
400 {
401 	return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0);
402 }
403 #endif
404 
405 int dram_init(void)
406 {
407 	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
408 				    CONFIG_SYS_SDRAM_SIZE);
409 	return 0;
410 }
411 
412 void reset_phy(void)
413 {
414 }
415 
416 static struct atmel_serial_platdata at91sam9260_serial_plat = {
417 	.base_addr = ATMEL_BASE_DBGU,
418 };
419 
420 U_BOOT_DEVICE(at91sam9260_serial) = {
421 	.name	= "serial_atmel",
422 	.platdata = &at91sam9260_serial_plat,
423 };
424