1c1393bb3SVeli-Pekka Peltola /* 2c1393bb3SVeli-Pekka Peltola * Bluegiga APX4 Development Kit 3c1393bb3SVeli-Pekka Peltola * 4c1393bb3SVeli-Pekka Peltola * Copyright (C) 2012 Bluegiga Technologies Oy 5c1393bb3SVeli-Pekka Peltola * 6c1393bb3SVeli-Pekka Peltola * Authors: 7c1393bb3SVeli-Pekka Peltola * Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com> 8c1393bb3SVeli-Pekka Peltola * Lauri Hintsala <lauri.hintsala@bluegiga.com> 9c1393bb3SVeli-Pekka Peltola * 10c1393bb3SVeli-Pekka Peltola * Based on spl_boot.c: 11c1393bb3SVeli-Pekka Peltola * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> 12c1393bb3SVeli-Pekka Peltola * on behalf of DENX Software Engineering GmbH 13c1393bb3SVeli-Pekka Peltola * 141a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 15c1393bb3SVeli-Pekka Peltola */ 16c1393bb3SVeli-Pekka Peltola 17c1393bb3SVeli-Pekka Peltola #include <common.h> 18c1393bb3SVeli-Pekka Peltola #include <config.h> 19c1393bb3SVeli-Pekka Peltola #include <asm/gpio.h> 20c1393bb3SVeli-Pekka Peltola #include <asm/io.h> 21c1393bb3SVeli-Pekka Peltola #include <asm/arch/iomux-mx28.h> 22c1393bb3SVeli-Pekka Peltola #include <asm/arch/imx-regs.h> 23c1393bb3SVeli-Pekka Peltola #include <asm/arch/sys_proto.h> 24c1393bb3SVeli-Pekka Peltola 25c1393bb3SVeli-Pekka Peltola #define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) 26c1393bb3SVeli-Pekka Peltola #define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) 27c1393bb3SVeli-Pekka Peltola #define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) 28c1393bb3SVeli-Pekka Peltola #define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) 29c1393bb3SVeli-Pekka Peltola 30c1393bb3SVeli-Pekka Peltola const iomux_cfg_t iomux_setup[] = { 31c1393bb3SVeli-Pekka Peltola /* DUART */ 32c1393bb3SVeli-Pekka Peltola MX28_PAD_PWM0__DUART_RX, 33c1393bb3SVeli-Pekka Peltola MX28_PAD_PWM1__DUART_TX, 34c1393bb3SVeli-Pekka Peltola 35c1393bb3SVeli-Pekka Peltola /* LED */ 36c1393bb3SVeli-Pekka Peltola MX28_PAD_PWM3__GPIO_3_28, 37c1393bb3SVeli-Pekka Peltola 38c1393bb3SVeli-Pekka Peltola /* MMC0 */ 39c1393bb3SVeli-Pekka Peltola MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0, 40c1393bb3SVeli-Pekka Peltola MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0, 41c1393bb3SVeli-Pekka Peltola MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0, 42c1393bb3SVeli-Pekka Peltola MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0, 43c1393bb3SVeli-Pekka Peltola MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0, 44c1393bb3SVeli-Pekka Peltola MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | 45c1393bb3SVeli-Pekka Peltola (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_NOPULL), 46c1393bb3SVeli-Pekka Peltola MX28_PAD_SSP0_SCK__SSP0_SCK | 47c1393bb3SVeli-Pekka Peltola (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), 48c1393bb3SVeli-Pekka Peltola 49c1393bb3SVeli-Pekka Peltola /* GPMI NAND */ 50c1393bb3SVeli-Pekka Peltola MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI, 51c1393bb3SVeli-Pekka Peltola MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI, 52c1393bb3SVeli-Pekka Peltola MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI, 53c1393bb3SVeli-Pekka Peltola MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI, 54c1393bb3SVeli-Pekka Peltola MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI, 55c1393bb3SVeli-Pekka Peltola MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI, 56c1393bb3SVeli-Pekka Peltola MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI, 57c1393bb3SVeli-Pekka Peltola MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI, 58c1393bb3SVeli-Pekka Peltola MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI, 59c1393bb3SVeli-Pekka Peltola MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI, 60c1393bb3SVeli-Pekka Peltola MX28_PAD_GPMI_RDN__GPMI_RDN | 61c1393bb3SVeli-Pekka Peltola (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), 62c1393bb3SVeli-Pekka Peltola MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI, 63c1393bb3SVeli-Pekka Peltola MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI, 64c1393bb3SVeli-Pekka Peltola MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI, 65c1393bb3SVeli-Pekka Peltola MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI, 66c1393bb3SVeli-Pekka Peltola 67c1393bb3SVeli-Pekka Peltola /* FEC0 */ 68c1393bb3SVeli-Pekka Peltola MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, 69c1393bb3SVeli-Pekka Peltola MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, 70c1393bb3SVeli-Pekka Peltola MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET, 71c1393bb3SVeli-Pekka Peltola MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET, 72c1393bb3SVeli-Pekka Peltola MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET, 73c1393bb3SVeli-Pekka Peltola MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET, 74c1393bb3SVeli-Pekka Peltola MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET, 75c1393bb3SVeli-Pekka Peltola MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET, 76c1393bb3SVeli-Pekka Peltola MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET, 77c1393bb3SVeli-Pekka Peltola 78c1393bb3SVeli-Pekka Peltola /* I2C */ 79c1393bb3SVeli-Pekka Peltola MX28_PAD_I2C0_SCL__I2C0_SCL, 80c1393bb3SVeli-Pekka Peltola MX28_PAD_I2C0_SDA__I2C0_SDA, 81c1393bb3SVeli-Pekka Peltola 82c1393bb3SVeli-Pekka Peltola /* EMI */ 83c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, 84c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, 85c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, 86c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, 87c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, 88c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, 89c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, 90c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, 91c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, 92c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, 93c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, 94c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, 95c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, 96c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, 97c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, 98c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, 99c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, 100c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, 101c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI, 102c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, 103c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, 104c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, 105c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, 106c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, 107c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, 108c1393bb3SVeli-Pekka Peltola 109c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, 110c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, 111c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, 112c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, 113c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, 114c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, 115c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, 116c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, 117c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, 118c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, 119c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, 120c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, 121c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, 122c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI, 123c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI, 124c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, 125c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, 126c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, 127c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, 128c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, 129c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, 130c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, 131c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, 132c1393bb3SVeli-Pekka Peltola MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, 133c1393bb3SVeli-Pekka Peltola }; 134c1393bb3SVeli-Pekka Peltola 135*7b8657e2SMarek Vasut void board_init_ll(const uint32_t arg, const uint32_t *resptr) 136c1393bb3SVeli-Pekka Peltola { 137*7b8657e2SMarek Vasut mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); 138c1393bb3SVeli-Pekka Peltola 139c1393bb3SVeli-Pekka Peltola /* switch LED on */ 140c1393bb3SVeli-Pekka Peltola gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0); 141c1393bb3SVeli-Pekka Peltola } 142c1393bb3SVeli-Pekka Peltola 1431e0cf5c3SOtavio Salvador void mxs_adjust_memory_params(uint32_t *dram_vals) 144c1393bb3SVeli-Pekka Peltola { 145c1393bb3SVeli-Pekka Peltola /* 146c1393bb3SVeli-Pekka Peltola * All address lines are routed from CPU to memory chip. 147c1393bb3SVeli-Pekka Peltola * ADDR_PINS field is set to zero. 148c1393bb3SVeli-Pekka Peltola */ 149c1393bb3SVeli-Pekka Peltola dram_vals[0x74 >> 2] = 0x0f02000a; 150c1393bb3SVeli-Pekka Peltola 151c1393bb3SVeli-Pekka Peltola /* Used memory has 4 banks. EIGHT_BANK_MODE bit is disabled. */ 152c1393bb3SVeli-Pekka Peltola dram_vals[0x7c >> 2] = 0x00000101; 153c1393bb3SVeli-Pekka Peltola } 154