1 /*
2  * Bluegiga APX4 Development Kit
3  *
4  * Copyright (C) 2012 Bluegiga Technologies Oy
5  *
6  * Authors:
7  * Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
8  * Lauri Hintsala <lauri.hintsala@bluegiga.com>
9  *
10  * Based on m28evk.c:
11  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
12  * on behalf of DENX Software Engineering GmbH
13  *
14  * See file CREDITS for list of people who contributed to this
15  * project.
16  *
17  * This program is free software; you can redistribute it and/or
18  * modify it under the terms of the GNU General Public License as
19  * published by the Free Software Foundation; either version 2 of
20  * the License, or (at your option) any later version.
21  *
22  * This program is distributed in the hope that it will be useful,
23  * but WITHOUT ANY WARRANTY; without even the implied warranty of
24  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
25  * GNU General Public License for more details.
26  */
27 
28 #include <common.h>
29 #include <asm/gpio.h>
30 #include <asm/io.h>
31 #include <asm/arch/imx-regs.h>
32 #include <asm/arch/iomux-mx28.h>
33 #include <asm/arch/clock.h>
34 #include <asm/arch/sys_proto.h>
35 #include <linux/mii.h>
36 #include <miiphy.h>
37 #include <netdev.h>
38 #include <errno.h>
39 
40 DECLARE_GLOBAL_DATA_PTR;
41 
42 /* Functions */
43 int board_early_init_f(void)
44 {
45 	/* IO0 clock at 480MHz */
46 	mxs_set_ioclk(MXC_IOCLK0, 480000);
47 	/* IO1 clock at 480MHz */
48 	mxs_set_ioclk(MXC_IOCLK1, 480000);
49 
50 	/* SSP0 clock at 96MHz */
51 	mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
52 
53 	return 0;
54 }
55 
56 int dram_init(void)
57 {
58 	return mxs_dram_init();
59 }
60 
61 int board_init(void)
62 {
63 	/* Adress of boot parameters */
64 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
65 
66 	return 0;
67 }
68 
69 #ifdef CONFIG_CMD_MMC
70 int board_mmc_init(bd_t *bis)
71 {
72 	return mxsmmc_initialize(bis, 0, NULL, NULL);
73 }
74 #endif
75 
76 
77 #ifdef CONFIG_CMD_NET
78 
79 #define MII_PHY_CTRL2 0x1f
80 int fecmxc_mii_postcall(int phy)
81 {
82 	/* change PHY RMII clock to 50MHz */
83 	miiphy_write("FEC", 0, MII_PHY_CTRL2, 0x8180);
84 
85 	return 0;
86 }
87 
88 int board_eth_init(bd_t *bis)
89 {
90 	int ret;
91 	struct eth_device *dev;
92 
93 	ret = cpu_eth_init(bis);
94 	if (ret) {
95 		printf("FEC MXS: Unable to init FEC clocks\n");
96 		return ret;
97 	}
98 
99 	ret = fecmxc_initialize(bis);
100 	if (ret) {
101 		printf("FEC MXS: Unable to init FEC\n");
102 		return ret;
103 	}
104 
105 	dev = eth_get_dev_by_name("FEC");
106 	if (!dev) {
107 		printf("FEC MXS: Unable to get FEC device entry\n");
108 		return -EINVAL;
109 	}
110 
111 	ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
112 	if (ret) {
113 		printf("FEC MXS: Unable to register FEC MII postcall\n");
114 		return ret;
115 	}
116 
117 	return ret;
118 }
119 #endif
120 
121 #ifdef CONFIG_SERIAL_TAG
122 #define MXS_OCOTP_MAX_TIMEOUT 1000000
123 void get_board_serial(struct tag_serialnr *serialnr)
124 {
125 	struct mxs_ocotp_regs *ocotp_regs =
126 		(struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
127 
128 	serialnr->high = 0;
129 	serialnr->low = 0;
130 
131 	writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
132 
133 	if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
134 		MXS_OCOTP_MAX_TIMEOUT)) {
135 		printf("MXS: Can't get serial number from OCOTP\n");
136 		return;
137 	}
138 
139 	serialnr->low = readl(&ocotp_regs->hw_ocotp_cust3);
140 }
141 #endif
142 
143 #ifdef CONFIG_REVISION_TAG
144 u32 get_board_rev(void)
145 {
146 	if (getenv("revision#") != NULL)
147 		return simple_strtoul(getenv("revision#"), NULL, 10);
148 	return 0;
149 }
150 #endif
151