1 /*
2  * Bluegiga APX4 Development Kit
3  *
4  * Copyright (C) 2012 Bluegiga Technologies Oy
5  *
6  * Authors:
7  * Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
8  * Lauri Hintsala <lauri.hintsala@bluegiga.com>
9  *
10  * Based on m28evk.c:
11  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
12  * on behalf of DENX Software Engineering GmbH
13  *
14  * SPDX-License-Identifier:	GPL-2.0+
15  */
16 
17 #include <common.h>
18 #include <asm/gpio.h>
19 #include <asm/io.h>
20 #include <asm/setup.h>
21 #include <asm/arch/imx-regs.h>
22 #include <asm/arch/iomux-mx28.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/sys_proto.h>
25 #include <linux/mii.h>
26 #include <miiphy.h>
27 #include <netdev.h>
28 #include <errno.h>
29 
30 DECLARE_GLOBAL_DATA_PTR;
31 
32 /* Functions */
33 int board_early_init_f(void)
34 {
35 	/* IO0 clock at 480MHz */
36 	mxs_set_ioclk(MXC_IOCLK0, 480000);
37 	/* IO1 clock at 480MHz */
38 	mxs_set_ioclk(MXC_IOCLK1, 480000);
39 
40 	/* SSP0 clock at 96MHz */
41 	mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
42 
43 	return 0;
44 }
45 
46 int dram_init(void)
47 {
48 	return mxs_dram_init();
49 }
50 
51 int board_init(void)
52 {
53 	/* Adress of boot parameters */
54 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
55 
56 	return 0;
57 }
58 
59 #ifdef CONFIG_CMD_MMC
60 int board_mmc_init(bd_t *bis)
61 {
62 	return mxsmmc_initialize(bis, 0, NULL, NULL);
63 }
64 #endif
65 
66 
67 #ifdef CONFIG_CMD_NET
68 
69 #define MII_PHY_CTRL2 0x1f
70 int fecmxc_mii_postcall(int phy)
71 {
72 	/* change PHY RMII clock to 50MHz */
73 	miiphy_write("FEC", 0, MII_PHY_CTRL2, 0x8180);
74 
75 	return 0;
76 }
77 
78 int board_eth_init(bd_t *bis)
79 {
80 	int ret;
81 	struct eth_device *dev;
82 
83 	ret = cpu_eth_init(bis);
84 	if (ret) {
85 		printf("FEC MXS: Unable to init FEC clocks\n");
86 		return ret;
87 	}
88 
89 	ret = fecmxc_initialize(bis);
90 	if (ret) {
91 		printf("FEC MXS: Unable to init FEC\n");
92 		return ret;
93 	}
94 
95 	dev = eth_get_dev_by_name("FEC");
96 	if (!dev) {
97 		printf("FEC MXS: Unable to get FEC device entry\n");
98 		return -EINVAL;
99 	}
100 
101 	ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
102 	if (ret) {
103 		printf("FEC MXS: Unable to register FEC MII postcall\n");
104 		return ret;
105 	}
106 
107 	return ret;
108 }
109 #endif
110 
111 #ifdef CONFIG_SERIAL_TAG
112 #define MXS_OCOTP_MAX_TIMEOUT 1000000
113 void get_board_serial(struct tag_serialnr *serialnr)
114 {
115 	struct mxs_ocotp_regs *ocotp_regs =
116 		(struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
117 
118 	serialnr->high = 0;
119 	serialnr->low = 0;
120 
121 	writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
122 
123 	if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
124 		MXS_OCOTP_MAX_TIMEOUT)) {
125 		printf("MXS: Can't get serial number from OCOTP\n");
126 		return;
127 	}
128 
129 	serialnr->low = readl(&ocotp_regs->hw_ocotp_cust3);
130 }
131 #endif
132 
133 #ifdef CONFIG_REVISION_TAG
134 u32 get_board_rev(void)
135 {
136 	if (getenv("revision#") != NULL)
137 		return simple_strtoul(getenv("revision#"), NULL, 10);
138 	return 0;
139 }
140 #endif
141