xref: /openbmc/u-boot/board/birdland/bav335x/board.c (revision f77d4410)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * board.c
4  *
5  * Board functions for Birdland Audio BAV335x Network Processor
6  *
7  * Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem
8  */
9 
10 #include <common.h>
11 #include <errno.h>
12 #include <spl.h>
13 #include <asm/arch/cpu.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/omap.h>
16 #include <asm/arch/ddr_defs.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/gpio.h>
19 #include <asm/arch/mmc_host_def.h>
20 #include <asm/arch/sys_proto.h>
21 #include <asm/arch/mem.h>
22 #include <asm/io.h>
23 #include <asm/emif.h>
24 #include <asm/gpio.h>
25 #include <i2c.h>
26 #include <miiphy.h>
27 #include <cpsw.h>
28 #include <power/tps65217.h>
29 #include <power/tps65910.h>
30 #include <environment.h>
31 #include <watchdog.h>
32 #include <environment.h>
33 #include "board.h"
34 
35 DECLARE_GLOBAL_DATA_PTR;
36 
37 /* GPIO that controls power to DDR on EVM-SK */
38 #define GPIO_DDR_VTT_EN		7
39 
40 static __maybe_unused struct ctrl_dev *cdev =
41 		(struct ctrl_dev *)CTRL_DEVICE_BASE;
42 
43 
44 
45 /*
46  * Read header information from EEPROM into global structure.
47  */
48 static int read_eeprom(struct board_eeconfig *header)
49 {
50 	/* Check if baseboard eeprom is available */
51 	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR))
52 		return -ENODEV;
53 
54 	/* read the eeprom using i2c */
55 	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
56 		     sizeof(struct board_eeconfig)))
57 		return -EIO;
58 
59 	if (header->magic != BOARD_MAGIC) {
60 		/* read the i2c eeprom again using only a 1 byte address */
61 		if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
62 			     sizeof(struct board_eeconfig)))
63 			return -EIO;
64 
65 		if (header->magic != BOARD_MAGIC)
66 			return -EINVAL;
67 	}
68 	return 0;
69 }
70 
71 
72 
73 
74 enum board_type get_board_type(bool debug)
75 {
76 	int ecode;
77 	struct board_eeconfig header;
78 
79 	ecode = read_eeprom(&header);
80 	if (ecode == 0) {
81 		if (header.version[1] == 'A') {
82 			if (debug)
83 				puts("=== Detected Board model BAV335x Rev.A");
84 			return BAV335A;
85 		} else if (header.version[1] == 'B') {
86 			if (debug)
87 				puts("=== Detected Board model BAV335x Rev.B");
88 			return BAV335B;
89 		} else if (debug) {
90 			puts("### Un-known board model in serial-EE\n");
91 		}
92 	} else if (debug) {
93 		switch (ecode) {
94 		case -ENODEV:
95 			puts("### Board doesn't have a serial-EE\n");
96 			break;
97 		case -EINVAL:
98 			puts("### Board serial-EE signature is incorrect.\n");
99 			break;
100 		default:
101 			puts("### IO Error reading serial-EE.\n");
102 			break;
103 		}
104 	}
105 
106 #if (CONFIG_BAV_VERSION == 1)
107 	if (debug)
108 		puts("### Selecting BAV335A as per config\n");
109 	return BAV335A;
110 #elif (CONFIG_BAV_VERSION == 2)
111 	if (debug)
112 		puts("### Selecting BAV335B as per config\n");
113 	return BAV335B;
114 #endif
115 #if (NOT_DEFINED == 2)
116 #error "SHOULD NEVER DISPLAY THIS"
117 #endif
118 
119 	if (debug)
120 		puts("### Defaulting to model BAV335x Rev.B\n");
121 	return BAV335B;
122 }
123 
124 
125 
126 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
127 static const struct ddr_data ddr3_bav335x_data = {
128 	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
129 	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
130 	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
131 	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
132 };
133 
134 static const struct cmd_control ddr3_bav335x_cmd_ctrl_data = {
135 	.cmd0csratio = MT41K256M16HA125E_RATIO,
136 	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
137 	.cmd1csratio = MT41K256M16HA125E_RATIO,
138 	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
139 	.cmd2csratio = MT41K256M16HA125E_RATIO,
140 	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
141 };
142 
143 
144 static struct emif_regs ddr3_bav335x_emif_reg_data = {
145 	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
146 	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
147 	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
148 	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
149 	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
150 	.zq_config = MT41K256M16HA125E_ZQ_CFG,
151 	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
152 };
153 
154 
155 #ifdef CONFIG_SPL_OS_BOOT
156 int spl_start_uboot(void)
157 {
158 	/* break into full u-boot on 'c' */
159 	if (serial_tstc() && serial_getc() == 'c')
160 		return 1;
161 
162 #ifdef CONFIG_SPL_ENV_SUPPORT
163 	env_init();
164 	env_load();
165 	if (env_get_yesno("boot_os") != 1)
166 		return 1;
167 #endif
168 
169 	return 0;
170 }
171 #endif
172 
173 #define OSC	(V_OSCK/1000000)
174 const struct dpll_params dpll_ddr = {
175 		266, OSC-1, 1, -1, -1, -1, -1};
176 const struct dpll_params dpll_ddr_evm_sk = {
177 		303, OSC-1, 1, -1, -1, -1, -1};
178 const struct dpll_params dpll_ddr_bone_black = {
179 		400, OSC-1, 1, -1, -1, -1, -1};
180 
181 void am33xx_spl_board_init(void)
182 {
183 	/* debug print detect status */
184 	(void)get_board_type(true);
185 
186 	/* Get the frequency */
187 	/* dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); */
188 	dpll_mpu_opp100.m = MPUPLL_M_1000;
189 
190 	if (i2c_probe(TPS65217_CHIP_PM))
191 		return;
192 
193 	/* Set the USB Current Limit */
194 	if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_POWER_PATH,
195 			       TPS65217_USB_INPUT_CUR_LIMIT_1800MA,
196 			       TPS65217_USB_INPUT_CUR_LIMIT_MASK))
197 		puts("! tps65217_reg_write: could not set USB limit\n");
198 
199 	/* Set the Core Voltage (DCDC3) to 1.125V */
200 	if (tps65217_voltage_update(TPS65217_DEFDCDC3,
201 				    TPS65217_DCDC_VOLT_SEL_1125MV)) {
202 		puts("! tps65217_reg_write: could not set Core Voltage\n");
203 		return;
204 	}
205 
206 	/* Set CORE Frequencies to OPP100 */
207 	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
208 
209 	/* Set the MPU Voltage (DCDC2) */
210 	if (tps65217_voltage_update(TPS65217_DEFDCDC2,
211 				    TPS65217_DCDC_VOLT_SEL_1325MV)) {
212 		puts("! tps65217_reg_write: could not set MPU Voltage\n");
213 		return;
214 	}
215 
216 	/*
217 	 * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
218 	 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
219 	 */
220 	if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS1,
221 			       TPS65217_LDO_VOLTAGE_OUT_1_8, TPS65217_LDO_MASK))
222 		puts("! tps65217_reg_write: could not set LDO3\n");
223 
224 	if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS2,
225 			       TPS65217_LDO_VOLTAGE_OUT_3_3, TPS65217_LDO_MASK))
226 		puts("! tps65217_reg_write: could not set LDO4\n");
227 
228 	/* Set MPU Frequency to what we detected now that voltages are set */
229 	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
230 }
231 
232 const struct dpll_params *get_dpll_ddr_params(void)
233 {
234 	enable_i2c0_pin_mux();
235 	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
236 
237 	return &dpll_ddr_bone_black;
238 }
239 
240 void set_uart_mux_conf(void)
241 {
242 #if CONFIG_CONS_INDEX == 1
243 	enable_uart0_pin_mux();
244 #elif CONFIG_CONS_INDEX == 2
245 	enable_uart1_pin_mux();
246 #elif CONFIG_CONS_INDEX == 3
247 	enable_uart2_pin_mux();
248 #elif CONFIG_CONS_INDEX == 4
249 	enable_uart3_pin_mux();
250 #elif CONFIG_CONS_INDEX == 5
251 	enable_uart4_pin_mux();
252 #elif CONFIG_CONS_INDEX == 6
253 	enable_uart5_pin_mux();
254 #endif
255 }
256 
257 void set_mux_conf_regs(void)
258 {
259 	enum board_type board;
260 
261 	board = get_board_type(false);
262 	enable_board_pin_mux(board);
263 }
264 
265 const struct ctrl_ioregs ioregs_bonelt = {
266 	.cm0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
267 	.cm1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
268 	.cm2ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
269 	.dt0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
270 	.dt1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
271 };
272 
273 
274 void sdram_init(void)
275 {
276 	config_ddr(400, &ioregs_bonelt,
277 		   &ddr3_bav335x_data,
278 		   &ddr3_bav335x_cmd_ctrl_data,
279 		   &ddr3_bav335x_emif_reg_data, 0);
280 }
281 #endif
282 
283 /*
284  * Basic board specific setup.  Pinmux has been handled already.
285  */
286 int board_init(void)
287 {
288 #if defined(CONFIG_HW_WATCHDOG)
289 	hw_watchdog_init();
290 #endif
291 
292 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
293 #if defined(CONFIG_NOR) || defined(CONFIG_NAND)
294 	gpmc_init();
295 #endif
296 	return 0;
297 }
298 
299 #ifdef CONFIG_BOARD_LATE_INIT
300 int board_late_init(void)
301 {
302 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
303 	env_set("board_name", "BAV335xB");
304 	env_set("board_rev", "B"); /* Fix me, but why bother.. */
305 #endif
306 	return 0;
307 }
308 #endif
309 
310 
311 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
312 	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
313 static void cpsw_control(int enabled)
314 {
315 	/* VTP can be added here */
316 	return;
317 }
318 
319 static struct cpsw_slave_data cpsw_slaves[] = {
320 	{
321 		.slave_reg_ofs	= 0x208,
322 		.sliver_reg_ofs	= 0xd80,
323 		.phy_addr	= 0,
324 	},
325 	{
326 		.slave_reg_ofs	= 0x308,
327 		.sliver_reg_ofs	= 0xdc0,
328 		.phy_addr	= 1,
329 	},
330 };
331 
332 static struct cpsw_platform_data cpsw_data = {
333 	.mdio_base		= CPSW_MDIO_BASE,
334 	.cpsw_base		= CPSW_BASE,
335 	.mdio_div		= 0xff,
336 	.channels		= 8,
337 	.cpdma_reg_ofs	= 0x800,
338 	.slaves			= 1,
339 	.slave_data		= cpsw_slaves,
340 	.ale_reg_ofs	= 0xd00,
341 	.ale_entries	= 1024,
342 	.host_port_reg_ofs	= 0x108,
343 	.hw_stats_reg_ofs	= 0x900,
344 	.bd_ram_ofs		= 0x2000,
345 	.mac_control	= (1 << 5),
346 	.control		= cpsw_control,
347 	.host_port_num	= 0,
348 	.version		= CPSW_CTRL_VERSION_2,
349 };
350 #endif
351 
352 
353 /*
354  * This function will:
355  * Perform fixups to the PHY present on certain boards.  We only need this
356  * function in:
357  * - SPL with either CPSW or USB ethernet support
358  * - Full U-Boot, with either CPSW or USB ethernet
359  * Build in only these cases to avoid warnings about unused variables
360  * when we build an SPL that has neither option but full U-Boot will.
361  */
362 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USB_ETHER)) &&\
363 		defined(CONFIG_SPL_BUILD)) || \
364 	((defined(CONFIG_DRIVER_TI_CPSW) || \
365 	  defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
366 	 !defined(CONFIG_SPL_BUILD))
367 int board_eth_init(bd_t *bis)
368 {
369 	int ecode, rv, n;
370 	uint8_t mac_addr[6];
371 	struct board_eeconfig header;
372 	__maybe_unused enum board_type board;
373 
374 	/* Default manufacturing address; used when no EE or invalid */
375 	n = 0;
376 	mac_addr[0] = 0;
377 	mac_addr[1] = 0x20;
378 	mac_addr[2] = 0x18;
379 	mac_addr[3] = 0x1C;
380 	mac_addr[4] = 0x00;
381 	mac_addr[5] = 0x01;
382 
383 	ecode = read_eeprom(&header);
384 	/* if we have a valid EE, get mac address from there */
385 	if ((ecode == 0) &&
386 	    is_valid_ethaddr((const u8 *)&header.mac_addr[0][0])) {
387 		memcpy(mac_addr, (const void *)&header.mac_addr[0][0], 6);
388 	}
389 
390 
391 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
392 	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
393 
394 	if (!env_get("ethaddr")) {
395 		printf("<ethaddr> not set. Validating first E-fuse MAC\n");
396 
397 		if (is_valid_ethaddr(mac_addr))
398 			eth_env_set_enetaddr("ethaddr", mac_addr);
399 	}
400 
401 #ifdef CONFIG_DRIVER_TI_CPSW
402 
403 	board = get_board_type(false);
404 
405 	/* Rev.A uses 10/100 PHY in mii mode */
406 	if (board == BAV335A) {
407 		writel(MII_MODE_ENABLE, &cdev->miisel);
408 		cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII;
409 		cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII;
410 	}
411 	/* Rev.B (default) uses GB PHY in rmii mode */
412 	else {
413 		writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
414 		cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if
415 				= PHY_INTERFACE_MODE_RGMII;
416 	}
417 
418 	rv = cpsw_register(&cpsw_data);
419 	if (rv < 0)
420 		printf("Error %d registering CPSW switch\n", rv);
421 	else
422 		n += rv;
423 #endif
424 
425 #endif
426 
427 	return n;
428 }
429 #endif
430