1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG
4 * Patrick Bruenn <p.bruenn@beckhoff.com>
5 *
6 * Based on <u-boot>/board/freescale/mx53loco/mx53loco.c
7 * Copyright (C) 2011 Freescale Semiconductor, Inc.
8 */
9
10 #include <common.h>
11 #include <dm.h>
12 #include <asm/io.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/sys_proto.h>
15 #include <asm/arch/crm_regs.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/iomux-mx53.h>
18 #include <asm/arch/clock.h>
19 #include <asm/mach-imx/mx5_video.h>
20 #include <ACEX1K.h>
21 #include <netdev.h>
22 #include <i2c.h>
23 #include <mmc.h>
24 #include <fsl_esdhc.h>
25 #include <asm/gpio.h>
26 #include <linux/fb.h>
27 #include <ipu_pixfmt.h>
28 #include <input.h>
29 #include <fs.h>
30 #include <dm/platform_data/serial_mxc.h>
31
32 enum LED_GPIOS {
33 GPIO_SD1_CD = IMX_GPIO_NR(1, 1),
34 GPIO_SD2_CD = IMX_GPIO_NR(1, 4),
35 GPIO_LED_SD2_R = IMX_GPIO_NR(3, 16),
36 GPIO_LED_SD2_B = IMX_GPIO_NR(3, 17),
37 GPIO_LED_SD2_G = IMX_GPIO_NR(3, 18),
38 GPIO_LED_SD1_R = IMX_GPIO_NR(3, 19),
39 GPIO_LED_SD1_B = IMX_GPIO_NR(3, 20),
40 GPIO_LED_SD1_G = IMX_GPIO_NR(3, 21),
41 GPIO_LED_PWR_R = IMX_GPIO_NR(3, 22),
42 GPIO_LED_PWR_B = IMX_GPIO_NR(3, 23),
43 GPIO_LED_PWR_G = IMX_GPIO_NR(3, 24),
44 GPIO_SUPS_INT = IMX_GPIO_NR(3, 31),
45 GPIO_C3_CONFIG = IMX_GPIO_NR(6, 8),
46 GPIO_C3_STATUS = IMX_GPIO_NR(6, 7),
47 GPIO_C3_DONE = IMX_GPIO_NR(6, 9),
48 };
49
50 #define CCAT_BASE_ADDR ((void *)0xf0000000)
51 #define CCAT_END_ADDR (CCAT_BASE_ADDR + (1024 * 1024 * 32))
52 #define CCAT_SIZE 1191788
53 #define CCAT_SIGN_ADDR (CCAT_BASE_ADDR + 12)
54 static const char CCAT_SIGNATURE[] = "CCAT";
55
56 static const u32 CCAT_MODE_CONFIG = 0x0024DC81;
57 static const u32 CCAT_MODE_RUN = 0x0033DC8F;
58
59 DECLARE_GLOBAL_DATA_PTR;
60
get_board_rev(void)61 u32 get_board_rev(void)
62 {
63 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
64 struct fuse_bank *bank = &iim->bank[0];
65 struct fuse_bank0_regs *fuse =
66 (struct fuse_bank0_regs *)bank->fuse_regs;
67
68 int rev = readl(&fuse->gp[6]);
69
70 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
71 }
72
73 /*
74 * Set CCAT mode
75 * @mode: use CCAT_MODE_CONFIG or CCAT_MODE_RUN
76 */
weim_cs0_settings(u32 mode)77 void weim_cs0_settings(u32 mode)
78 {
79 struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
80
81 writel(0x0, &weim_regs->cs0gcr1);
82 writel(mode, &weim_regs->cs0gcr1);
83 writel(0x00001002, &weim_regs->cs0gcr2);
84
85 writel(0x04000000, &weim_regs->cs0rcr1);
86 writel(0x00000000, &weim_regs->cs0rcr2);
87
88 writel(0x04000000, &weim_regs->cs0wcr1);
89 writel(0x00000000, &weim_regs->cs0wcr2);
90 }
91
setup_gpio_eim(void)92 static void setup_gpio_eim(void)
93 {
94 gpio_direction_input(GPIO_C3_STATUS);
95 gpio_direction_input(GPIO_C3_DONE);
96 gpio_direction_output(GPIO_C3_CONFIG, 1);
97
98 weim_cs0_settings(CCAT_MODE_RUN);
99 }
100
setup_gpio_sups(void)101 static void setup_gpio_sups(void)
102 {
103 gpio_direction_input(GPIO_SUPS_INT);
104
105 static const int BLINK_INTERVALL = 50000;
106 int status = 1;
107 while (gpio_get_value(GPIO_SUPS_INT)) {
108 /* signal "CX SUPS power fail" */
109 gpio_set_value(GPIO_LED_PWR_R,
110 (++status / BLINK_INTERVALL) % 2);
111 }
112
113 /* signal "CX power up" */
114 gpio_set_value(GPIO_LED_PWR_R, 1);
115 }
116
setup_gpio_leds(void)117 static void setup_gpio_leds(void)
118 {
119 gpio_direction_output(GPIO_LED_SD2_R, 0);
120 gpio_direction_output(GPIO_LED_SD2_B, 0);
121 gpio_direction_output(GPIO_LED_SD2_G, 0);
122 gpio_direction_output(GPIO_LED_SD1_R, 0);
123 gpio_direction_output(GPIO_LED_SD1_B, 0);
124 gpio_direction_output(GPIO_LED_SD1_G, 0);
125 gpio_direction_output(GPIO_LED_PWR_R, 0);
126 gpio_direction_output(GPIO_LED_PWR_B, 0);
127 gpio_direction_output(GPIO_LED_PWR_G, 0);
128 }
129
130 #ifdef CONFIG_USB_EHCI_MX5
board_ehci_hcd_init(int port)131 int board_ehci_hcd_init(int port)
132 {
133 /* request VBUS power enable pin, GPIO7_8 */
134 gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
135 return 0;
136 }
137 #endif
138
139 #ifdef CONFIG_FSL_ESDHC
140 struct fsl_esdhc_cfg esdhc_cfg[2] = {
141 {MMC_SDHC1_BASE_ADDR},
142 {MMC_SDHC2_BASE_ADDR},
143 };
144
board_mmc_getcd(struct mmc * mmc)145 int board_mmc_getcd(struct mmc *mmc)
146 {
147 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
148 int ret;
149
150 gpio_direction_input(GPIO_SD1_CD);
151 gpio_direction_input(GPIO_SD2_CD);
152
153 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
154 ret = !gpio_get_value(GPIO_SD1_CD);
155 else
156 ret = !gpio_get_value(GPIO_SD2_CD);
157
158 return ret;
159 }
160
board_mmc_init(bd_t * bis)161 int board_mmc_init(bd_t *bis)
162 {
163 u32 index;
164 int ret;
165
166 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
167 esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
168
169 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
170 switch (index) {
171 case 0:
172 break;
173 case 1:
174 break;
175 default:
176 printf("Warning: you configured more ESDHC controller(%d) as supported by the board(2)\n",
177 CONFIG_SYS_FSL_ESDHC_NUM);
178 return -EINVAL;
179 }
180 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
181 if (ret)
182 return ret;
183 }
184
185 return 0;
186 }
187 #endif
188
power_init(void)189 static int power_init(void)
190 {
191 /* nothing to do on CX9020 */
192 return 0;
193 }
194
clock_1GHz(void)195 static void clock_1GHz(void)
196 {
197 int ret;
198 u32 ref_clk = MXC_HCLK;
199 /*
200 * After increasing voltage to 1.25V, we can switch
201 * CPU clock to 1GHz and DDR to 400MHz safely
202 */
203 ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
204 if (ret)
205 printf("CPU: Switch CPU clock to 1GHZ failed\n");
206
207 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
208 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
209 if (ret)
210 printf("CPU: Switch DDR clock to 400MHz failed\n");
211 }
212
board_early_init_f(void)213 int board_early_init_f(void)
214 {
215 setup_gpio_leds();
216 setup_gpio_sups();
217 setup_gpio_eim();
218 setup_iomux_lcd();
219
220 return 0;
221 }
222
223 /*
224 * Do not overwrite the console
225 * Use always serial for U-Boot console
226 */
overwrite_console(void)227 int overwrite_console(void)
228 {
229 return 1;
230 }
231
board_init(void)232 int board_init(void)
233 {
234 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
235
236 mxc_set_sata_internal_clock();
237
238 return 0;
239 }
240
checkboard(void)241 int checkboard(void)
242 {
243 puts("Board: Beckhoff CX9020\n");
244
245 return 0;
246 }
247
ccat_config_fn(int assert_config,int flush,int cookie)248 static int ccat_config_fn(int assert_config, int flush, int cookie)
249 {
250 /* prepare FPGA for programming */
251 weim_cs0_settings(CCAT_MODE_CONFIG);
252 gpio_set_value(GPIO_C3_CONFIG, 0);
253 udelay(1);
254 gpio_set_value(GPIO_C3_CONFIG, 1);
255 udelay(230);
256
257 return FPGA_SUCCESS;
258 }
259
ccat_status_fn(int cookie)260 static int ccat_status_fn(int cookie)
261 {
262 return FPGA_FAIL;
263 }
264
ccat_write_fn(const void * buf,size_t buf_len,int flush,int cookie)265 static int ccat_write_fn(const void *buf, size_t buf_len, int flush, int cookie)
266 {
267 const uint8_t *const buffer = buf;
268
269 /* program CCAT */
270 int i;
271 for (i = 0; i < buf_len; ++i)
272 writeb(buffer[i], CCAT_BASE_ADDR);
273
274 writeb(0xff, CCAT_BASE_ADDR);
275 writeb(0xff, CCAT_BASE_ADDR);
276
277 return FPGA_SUCCESS;
278 }
279
ccat_done_fn(int cookie)280 static int ccat_done_fn(int cookie)
281 {
282 /* programming complete? */
283 return gpio_get_value(GPIO_C3_DONE);
284 }
285
ccat_post_fn(int cookie)286 static int ccat_post_fn(int cookie)
287 {
288 /* switch to FPGA run mode */
289 weim_cs0_settings(CCAT_MODE_RUN);
290 invalidate_dcache_range((ulong) CCAT_BASE_ADDR, (ulong) CCAT_END_ADDR);
291
292 if (memcmp(CCAT_SIGN_ADDR, CCAT_SIGNATURE, sizeof(CCAT_SIGNATURE))) {
293 printf("Verifing CCAT firmware failed, signature not found\n");
294 return FPGA_FAIL;
295 }
296
297 /* signal "CX booting OS" */
298 gpio_set_value(GPIO_LED_PWR_R, 1);
299 gpio_set_value(GPIO_LED_PWR_G, 1);
300 gpio_set_value(GPIO_LED_PWR_B, 0);
301 return FPGA_SUCCESS;
302 }
303
304 static Altera_CYC2_Passive_Serial_fns ccat_fns = {
305 .config = ccat_config_fn,
306 .status = ccat_status_fn,
307 .done = ccat_done_fn,
308 .write = ccat_write_fn,
309 .abort = ccat_post_fn,
310 .post = ccat_post_fn,
311 };
312
313 static Altera_desc ccat_fpga = {
314 .family = Altera_CYC2,
315 .iface = passive_serial,
316 .size = CCAT_SIZE,
317 .iface_fns = &ccat_fns,
318 .base = CCAT_BASE_ADDR,
319 };
320
board_late_init(void)321 int board_late_init(void)
322 {
323 if (!power_init())
324 clock_1GHz();
325
326 fpga_init();
327 fpga_add(fpga_altera, &ccat_fpga);
328
329 return 0;
330 }
331