1*98d62e61SPatrick Bruenn /* 2*98d62e61SPatrick Bruenn * Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG 3*98d62e61SPatrick Bruenn * Patrick Bruenn <p.bruenn@beckhoff.com> 4*98d62e61SPatrick Bruenn * 5*98d62e61SPatrick Bruenn * Based on <u-boot>/board/freescale/mx53loco/mx53loco.c 6*98d62e61SPatrick Bruenn * Copyright (C) 2011 Freescale Semiconductor, Inc. 7*98d62e61SPatrick Bruenn * 8*98d62e61SPatrick Bruenn * SPDX-License-Identifier: GPL-2.0+ 9*98d62e61SPatrick Bruenn */ 10*98d62e61SPatrick Bruenn 11*98d62e61SPatrick Bruenn #include <common.h> 12*98d62e61SPatrick Bruenn #include <asm/io.h> 13*98d62e61SPatrick Bruenn #include <asm/arch/imx-regs.h> 14*98d62e61SPatrick Bruenn #include <asm/arch/sys_proto.h> 15*98d62e61SPatrick Bruenn #include <asm/arch/crm_regs.h> 16*98d62e61SPatrick Bruenn #include <asm/arch/clock.h> 17*98d62e61SPatrick Bruenn #include <asm/arch/iomux-mx53.h> 18*98d62e61SPatrick Bruenn #include <asm/arch/clock.h> 19*98d62e61SPatrick Bruenn #include <asm/imx-common/mx5_video.h> 20*98d62e61SPatrick Bruenn #include <ACEX1K.h> 21*98d62e61SPatrick Bruenn #include <netdev.h> 22*98d62e61SPatrick Bruenn #include <i2c.h> 23*98d62e61SPatrick Bruenn #include <mmc.h> 24*98d62e61SPatrick Bruenn #include <fsl_esdhc.h> 25*98d62e61SPatrick Bruenn #include <asm/gpio.h> 26*98d62e61SPatrick Bruenn #include <linux/fb.h> 27*98d62e61SPatrick Bruenn #include <ipu_pixfmt.h> 28*98d62e61SPatrick Bruenn #include <fs.h> 29*98d62e61SPatrick Bruenn #include <dm/platdata.h> 30*98d62e61SPatrick Bruenn #include <dm/platform_data/serial_mxc.h> 31*98d62e61SPatrick Bruenn 32*98d62e61SPatrick Bruenn enum LED_GPIOS { 33*98d62e61SPatrick Bruenn GPIO_SD1_CD = IMX_GPIO_NR(1, 1), 34*98d62e61SPatrick Bruenn GPIO_SD2_CD = IMX_GPIO_NR(1, 4), 35*98d62e61SPatrick Bruenn GPIO_LED_SD2_R = IMX_GPIO_NR(3, 16), 36*98d62e61SPatrick Bruenn GPIO_LED_SD2_B = IMX_GPIO_NR(3, 17), 37*98d62e61SPatrick Bruenn GPIO_LED_SD2_G = IMX_GPIO_NR(3, 18), 38*98d62e61SPatrick Bruenn GPIO_LED_SD1_R = IMX_GPIO_NR(3, 19), 39*98d62e61SPatrick Bruenn GPIO_LED_SD1_B = IMX_GPIO_NR(3, 20), 40*98d62e61SPatrick Bruenn GPIO_LED_SD1_G = IMX_GPIO_NR(3, 21), 41*98d62e61SPatrick Bruenn GPIO_LED_PWR_R = IMX_GPIO_NR(3, 22), 42*98d62e61SPatrick Bruenn GPIO_LED_PWR_B = IMX_GPIO_NR(3, 23), 43*98d62e61SPatrick Bruenn GPIO_LED_PWR_G = IMX_GPIO_NR(3, 24), 44*98d62e61SPatrick Bruenn GPIO_SUPS_INT = IMX_GPIO_NR(3, 31), 45*98d62e61SPatrick Bruenn GPIO_C3_CONFIG = IMX_GPIO_NR(6, 8), 46*98d62e61SPatrick Bruenn GPIO_C3_STATUS = IMX_GPIO_NR(6, 7), 47*98d62e61SPatrick Bruenn GPIO_C3_DONE = IMX_GPIO_NR(6, 9), 48*98d62e61SPatrick Bruenn }; 49*98d62e61SPatrick Bruenn 50*98d62e61SPatrick Bruenn #define CCAT_BASE_ADDR ((void *)0xf0000000) 51*98d62e61SPatrick Bruenn #define CCAT_END_ADDR (CCAT_BASE_ADDR + (1024 * 1024 * 32)) 52*98d62e61SPatrick Bruenn #define CCAT_SIZE 1191788 53*98d62e61SPatrick Bruenn #define CCAT_SIGN_ADDR (CCAT_BASE_ADDR + 12) 54*98d62e61SPatrick Bruenn static const char CCAT_SIGNATURE[] = "CCAT"; 55*98d62e61SPatrick Bruenn 56*98d62e61SPatrick Bruenn static const u32 CCAT_MODE_CONFIG = 0x0024DC81; 57*98d62e61SPatrick Bruenn static const u32 CCAT_MODE_RUN = 0x0033DC8F; 58*98d62e61SPatrick Bruenn 59*98d62e61SPatrick Bruenn DECLARE_GLOBAL_DATA_PTR; 60*98d62e61SPatrick Bruenn 61*98d62e61SPatrick Bruenn static uint32_t mx53_dram_size[2]; 62*98d62e61SPatrick Bruenn 63*98d62e61SPatrick Bruenn phys_size_t get_effective_memsize(void) 64*98d62e61SPatrick Bruenn { 65*98d62e61SPatrick Bruenn /* 66*98d62e61SPatrick Bruenn * WARNING: We must override get_effective_memsize() function here 67*98d62e61SPatrick Bruenn * to report only the size of the first DRAM bank. This is to make 68*98d62e61SPatrick Bruenn * U-Boot relocator place U-Boot into valid memory, that is, at the 69*98d62e61SPatrick Bruenn * end of the first DRAM bank. If we did not override this function 70*98d62e61SPatrick Bruenn * like so, U-Boot would be placed at the address of the first DRAM 71*98d62e61SPatrick Bruenn * bank + total DRAM size - sizeof(uboot), which in the setup where 72*98d62e61SPatrick Bruenn * each DRAM bank contains 512MiB of DRAM would result in placing 73*98d62e61SPatrick Bruenn * U-Boot into invalid memory area close to the end of the first 74*98d62e61SPatrick Bruenn * DRAM bank. 75*98d62e61SPatrick Bruenn */ 76*98d62e61SPatrick Bruenn return mx53_dram_size[0]; 77*98d62e61SPatrick Bruenn } 78*98d62e61SPatrick Bruenn 79*98d62e61SPatrick Bruenn int dram_init(void) 80*98d62e61SPatrick Bruenn { 81*98d62e61SPatrick Bruenn mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30); 82*98d62e61SPatrick Bruenn mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30); 83*98d62e61SPatrick Bruenn 84*98d62e61SPatrick Bruenn gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1]; 85*98d62e61SPatrick Bruenn 86*98d62e61SPatrick Bruenn return 0; 87*98d62e61SPatrick Bruenn } 88*98d62e61SPatrick Bruenn 89*98d62e61SPatrick Bruenn void dram_init_banksize(void) 90*98d62e61SPatrick Bruenn { 91*98d62e61SPatrick Bruenn gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 92*98d62e61SPatrick Bruenn gd->bd->bi_dram[0].size = mx53_dram_size[0]; 93*98d62e61SPatrick Bruenn 94*98d62e61SPatrick Bruenn gd->bd->bi_dram[1].start = PHYS_SDRAM_2; 95*98d62e61SPatrick Bruenn gd->bd->bi_dram[1].size = mx53_dram_size[1]; 96*98d62e61SPatrick Bruenn } 97*98d62e61SPatrick Bruenn 98*98d62e61SPatrick Bruenn u32 get_board_rev(void) 99*98d62e61SPatrick Bruenn { 100*98d62e61SPatrick Bruenn struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; 101*98d62e61SPatrick Bruenn struct fuse_bank *bank = &iim->bank[0]; 102*98d62e61SPatrick Bruenn struct fuse_bank0_regs *fuse = 103*98d62e61SPatrick Bruenn (struct fuse_bank0_regs *)bank->fuse_regs; 104*98d62e61SPatrick Bruenn 105*98d62e61SPatrick Bruenn int rev = readl(&fuse->gp[6]); 106*98d62e61SPatrick Bruenn 107*98d62e61SPatrick Bruenn return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; 108*98d62e61SPatrick Bruenn } 109*98d62e61SPatrick Bruenn 110*98d62e61SPatrick Bruenn /* 111*98d62e61SPatrick Bruenn * Set CCAT mode 112*98d62e61SPatrick Bruenn * @mode: use CCAT_MODE_CONFIG or CCAT_MODE_RUN 113*98d62e61SPatrick Bruenn */ 114*98d62e61SPatrick Bruenn void weim_cs0_settings(u32 mode) 115*98d62e61SPatrick Bruenn { 116*98d62e61SPatrick Bruenn struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR; 117*98d62e61SPatrick Bruenn 118*98d62e61SPatrick Bruenn writel(0x0, &weim_regs->cs0gcr1); 119*98d62e61SPatrick Bruenn writel(mode, &weim_regs->cs0gcr1); 120*98d62e61SPatrick Bruenn writel(0x00001002, &weim_regs->cs0gcr2); 121*98d62e61SPatrick Bruenn 122*98d62e61SPatrick Bruenn writel(0x04000000, &weim_regs->cs0rcr1); 123*98d62e61SPatrick Bruenn writel(0x00000000, &weim_regs->cs0rcr2); 124*98d62e61SPatrick Bruenn 125*98d62e61SPatrick Bruenn writel(0x04000000, &weim_regs->cs0wcr1); 126*98d62e61SPatrick Bruenn writel(0x00000000, &weim_regs->cs0wcr2); 127*98d62e61SPatrick Bruenn } 128*98d62e61SPatrick Bruenn 129*98d62e61SPatrick Bruenn static void setup_gpio_eim(void) 130*98d62e61SPatrick Bruenn { 131*98d62e61SPatrick Bruenn gpio_direction_input(GPIO_C3_STATUS); 132*98d62e61SPatrick Bruenn gpio_direction_input(GPIO_C3_DONE); 133*98d62e61SPatrick Bruenn gpio_direction_output(GPIO_C3_CONFIG, 1); 134*98d62e61SPatrick Bruenn 135*98d62e61SPatrick Bruenn weim_cs0_settings(CCAT_MODE_RUN); 136*98d62e61SPatrick Bruenn } 137*98d62e61SPatrick Bruenn 138*98d62e61SPatrick Bruenn static void setup_gpio_sups(void) 139*98d62e61SPatrick Bruenn { 140*98d62e61SPatrick Bruenn gpio_direction_input(GPIO_SUPS_INT); 141*98d62e61SPatrick Bruenn 142*98d62e61SPatrick Bruenn static const int BLINK_INTERVALL = 50000; 143*98d62e61SPatrick Bruenn int status = 1; 144*98d62e61SPatrick Bruenn while (gpio_get_value(GPIO_SUPS_INT)) { 145*98d62e61SPatrick Bruenn /* signal "CX SUPS power fail" */ 146*98d62e61SPatrick Bruenn gpio_set_value(GPIO_LED_PWR_R, 147*98d62e61SPatrick Bruenn (++status / BLINK_INTERVALL) % 2); 148*98d62e61SPatrick Bruenn } 149*98d62e61SPatrick Bruenn 150*98d62e61SPatrick Bruenn /* signal "CX power up" */ 151*98d62e61SPatrick Bruenn gpio_set_value(GPIO_LED_PWR_R, 1); 152*98d62e61SPatrick Bruenn } 153*98d62e61SPatrick Bruenn 154*98d62e61SPatrick Bruenn static void setup_gpio_leds(void) 155*98d62e61SPatrick Bruenn { 156*98d62e61SPatrick Bruenn gpio_direction_output(GPIO_LED_SD2_R, 0); 157*98d62e61SPatrick Bruenn gpio_direction_output(GPIO_LED_SD2_B, 0); 158*98d62e61SPatrick Bruenn gpio_direction_output(GPIO_LED_SD2_G, 0); 159*98d62e61SPatrick Bruenn gpio_direction_output(GPIO_LED_SD1_R, 0); 160*98d62e61SPatrick Bruenn gpio_direction_output(GPIO_LED_SD1_B, 0); 161*98d62e61SPatrick Bruenn gpio_direction_output(GPIO_LED_SD1_G, 0); 162*98d62e61SPatrick Bruenn gpio_direction_output(GPIO_LED_PWR_R, 0); 163*98d62e61SPatrick Bruenn gpio_direction_output(GPIO_LED_PWR_B, 0); 164*98d62e61SPatrick Bruenn gpio_direction_output(GPIO_LED_PWR_G, 0); 165*98d62e61SPatrick Bruenn } 166*98d62e61SPatrick Bruenn 167*98d62e61SPatrick Bruenn #ifdef CONFIG_USB_EHCI_MX5 168*98d62e61SPatrick Bruenn int board_ehci_hcd_init(int port) 169*98d62e61SPatrick Bruenn { 170*98d62e61SPatrick Bruenn /* request VBUS power enable pin, GPIO7_8 */ 171*98d62e61SPatrick Bruenn gpio_direction_output(IMX_GPIO_NR(7, 8), 1); 172*98d62e61SPatrick Bruenn return 0; 173*98d62e61SPatrick Bruenn } 174*98d62e61SPatrick Bruenn #endif 175*98d62e61SPatrick Bruenn 176*98d62e61SPatrick Bruenn #ifdef CONFIG_FSL_ESDHC 177*98d62e61SPatrick Bruenn struct fsl_esdhc_cfg esdhc_cfg[2] = { 178*98d62e61SPatrick Bruenn {MMC_SDHC1_BASE_ADDR}, 179*98d62e61SPatrick Bruenn {MMC_SDHC2_BASE_ADDR}, 180*98d62e61SPatrick Bruenn }; 181*98d62e61SPatrick Bruenn 182*98d62e61SPatrick Bruenn int board_mmc_getcd(struct mmc *mmc) 183*98d62e61SPatrick Bruenn { 184*98d62e61SPatrick Bruenn struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 185*98d62e61SPatrick Bruenn int ret; 186*98d62e61SPatrick Bruenn 187*98d62e61SPatrick Bruenn gpio_direction_input(GPIO_SD1_CD); 188*98d62e61SPatrick Bruenn gpio_direction_input(GPIO_SD2_CD); 189*98d62e61SPatrick Bruenn 190*98d62e61SPatrick Bruenn if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) 191*98d62e61SPatrick Bruenn ret = !gpio_get_value(GPIO_SD1_CD); 192*98d62e61SPatrick Bruenn else 193*98d62e61SPatrick Bruenn ret = !gpio_get_value(GPIO_SD2_CD); 194*98d62e61SPatrick Bruenn 195*98d62e61SPatrick Bruenn return ret; 196*98d62e61SPatrick Bruenn } 197*98d62e61SPatrick Bruenn 198*98d62e61SPatrick Bruenn int board_mmc_init(bd_t *bis) 199*98d62e61SPatrick Bruenn { 200*98d62e61SPatrick Bruenn u32 index; 201*98d62e61SPatrick Bruenn int ret; 202*98d62e61SPatrick Bruenn 203*98d62e61SPatrick Bruenn esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 204*98d62e61SPatrick Bruenn esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 205*98d62e61SPatrick Bruenn 206*98d62e61SPatrick Bruenn for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { 207*98d62e61SPatrick Bruenn switch (index) { 208*98d62e61SPatrick Bruenn case 0: 209*98d62e61SPatrick Bruenn break; 210*98d62e61SPatrick Bruenn case 1: 211*98d62e61SPatrick Bruenn break; 212*98d62e61SPatrick Bruenn default: 213*98d62e61SPatrick Bruenn printf("Warning: you configured more ESDHC controller(%d) as supported by the board(2)\n", 214*98d62e61SPatrick Bruenn CONFIG_SYS_FSL_ESDHC_NUM); 215*98d62e61SPatrick Bruenn return -EINVAL; 216*98d62e61SPatrick Bruenn } 217*98d62e61SPatrick Bruenn ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]); 218*98d62e61SPatrick Bruenn if (ret) 219*98d62e61SPatrick Bruenn return ret; 220*98d62e61SPatrick Bruenn } 221*98d62e61SPatrick Bruenn 222*98d62e61SPatrick Bruenn return 0; 223*98d62e61SPatrick Bruenn } 224*98d62e61SPatrick Bruenn #endif 225*98d62e61SPatrick Bruenn 226*98d62e61SPatrick Bruenn static int power_init(void) 227*98d62e61SPatrick Bruenn { 228*98d62e61SPatrick Bruenn /* nothing to do on CX9020 */ 229*98d62e61SPatrick Bruenn return 0; 230*98d62e61SPatrick Bruenn } 231*98d62e61SPatrick Bruenn 232*98d62e61SPatrick Bruenn static void clock_1GHz(void) 233*98d62e61SPatrick Bruenn { 234*98d62e61SPatrick Bruenn int ret; 235*98d62e61SPatrick Bruenn u32 ref_clk = MXC_HCLK; 236*98d62e61SPatrick Bruenn /* 237*98d62e61SPatrick Bruenn * After increasing voltage to 1.25V, we can switch 238*98d62e61SPatrick Bruenn * CPU clock to 1GHz and DDR to 400MHz safely 239*98d62e61SPatrick Bruenn */ 240*98d62e61SPatrick Bruenn ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK); 241*98d62e61SPatrick Bruenn if (ret) 242*98d62e61SPatrick Bruenn printf("CPU: Switch CPU clock to 1GHZ failed\n"); 243*98d62e61SPatrick Bruenn 244*98d62e61SPatrick Bruenn ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); 245*98d62e61SPatrick Bruenn ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK); 246*98d62e61SPatrick Bruenn if (ret) 247*98d62e61SPatrick Bruenn printf("CPU: Switch DDR clock to 400MHz failed\n"); 248*98d62e61SPatrick Bruenn } 249*98d62e61SPatrick Bruenn 250*98d62e61SPatrick Bruenn int board_early_init_f(void) 251*98d62e61SPatrick Bruenn { 252*98d62e61SPatrick Bruenn setup_gpio_leds(); 253*98d62e61SPatrick Bruenn setup_gpio_sups(); 254*98d62e61SPatrick Bruenn setup_gpio_eim(); 255*98d62e61SPatrick Bruenn setup_iomux_lcd(); 256*98d62e61SPatrick Bruenn 257*98d62e61SPatrick Bruenn return 0; 258*98d62e61SPatrick Bruenn } 259*98d62e61SPatrick Bruenn 260*98d62e61SPatrick Bruenn /* 261*98d62e61SPatrick Bruenn * Do not overwrite the console 262*98d62e61SPatrick Bruenn * Use always serial for U-Boot console 263*98d62e61SPatrick Bruenn */ 264*98d62e61SPatrick Bruenn int overwrite_console(void) 265*98d62e61SPatrick Bruenn { 266*98d62e61SPatrick Bruenn return 1; 267*98d62e61SPatrick Bruenn } 268*98d62e61SPatrick Bruenn 269*98d62e61SPatrick Bruenn int board_init(void) 270*98d62e61SPatrick Bruenn { 271*98d62e61SPatrick Bruenn gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 272*98d62e61SPatrick Bruenn 273*98d62e61SPatrick Bruenn mxc_set_sata_internal_clock(); 274*98d62e61SPatrick Bruenn 275*98d62e61SPatrick Bruenn return 0; 276*98d62e61SPatrick Bruenn } 277*98d62e61SPatrick Bruenn 278*98d62e61SPatrick Bruenn int checkboard(void) 279*98d62e61SPatrick Bruenn { 280*98d62e61SPatrick Bruenn puts("Board: Beckhoff CX9020\n"); 281*98d62e61SPatrick Bruenn 282*98d62e61SPatrick Bruenn return 0; 283*98d62e61SPatrick Bruenn } 284*98d62e61SPatrick Bruenn 285*98d62e61SPatrick Bruenn static int ccat_config_fn(int assert_config, int flush, int cookie) 286*98d62e61SPatrick Bruenn { 287*98d62e61SPatrick Bruenn /* prepare FPGA for programming */ 288*98d62e61SPatrick Bruenn weim_cs0_settings(CCAT_MODE_CONFIG); 289*98d62e61SPatrick Bruenn gpio_set_value(GPIO_C3_CONFIG, 0); 290*98d62e61SPatrick Bruenn udelay(1); 291*98d62e61SPatrick Bruenn gpio_set_value(GPIO_C3_CONFIG, 1); 292*98d62e61SPatrick Bruenn udelay(230); 293*98d62e61SPatrick Bruenn 294*98d62e61SPatrick Bruenn return FPGA_SUCCESS; 295*98d62e61SPatrick Bruenn } 296*98d62e61SPatrick Bruenn 297*98d62e61SPatrick Bruenn static int ccat_status_fn(int cookie) 298*98d62e61SPatrick Bruenn { 299*98d62e61SPatrick Bruenn return FPGA_FAIL; 300*98d62e61SPatrick Bruenn } 301*98d62e61SPatrick Bruenn 302*98d62e61SPatrick Bruenn static int ccat_write_fn(const void *buf, size_t buf_len, int flush, int cookie) 303*98d62e61SPatrick Bruenn { 304*98d62e61SPatrick Bruenn const uint8_t *const buffer = buf; 305*98d62e61SPatrick Bruenn 306*98d62e61SPatrick Bruenn /* program CCAT */ 307*98d62e61SPatrick Bruenn int i; 308*98d62e61SPatrick Bruenn for (i = 0; i < buf_len; ++i) 309*98d62e61SPatrick Bruenn writeb(buffer[i], CCAT_BASE_ADDR); 310*98d62e61SPatrick Bruenn 311*98d62e61SPatrick Bruenn writeb(0xff, CCAT_BASE_ADDR); 312*98d62e61SPatrick Bruenn writeb(0xff, CCAT_BASE_ADDR); 313*98d62e61SPatrick Bruenn 314*98d62e61SPatrick Bruenn return FPGA_SUCCESS; 315*98d62e61SPatrick Bruenn } 316*98d62e61SPatrick Bruenn 317*98d62e61SPatrick Bruenn static int ccat_done_fn(int cookie) 318*98d62e61SPatrick Bruenn { 319*98d62e61SPatrick Bruenn /* programming complete? */ 320*98d62e61SPatrick Bruenn return gpio_get_value(GPIO_C3_DONE); 321*98d62e61SPatrick Bruenn } 322*98d62e61SPatrick Bruenn 323*98d62e61SPatrick Bruenn static int ccat_post_fn(int cookie) 324*98d62e61SPatrick Bruenn { 325*98d62e61SPatrick Bruenn /* switch to FPGA run mode */ 326*98d62e61SPatrick Bruenn weim_cs0_settings(CCAT_MODE_RUN); 327*98d62e61SPatrick Bruenn invalidate_dcache_range((ulong) CCAT_BASE_ADDR, (ulong) CCAT_END_ADDR); 328*98d62e61SPatrick Bruenn 329*98d62e61SPatrick Bruenn if (memcmp(CCAT_SIGN_ADDR, CCAT_SIGNATURE, sizeof(CCAT_SIGNATURE))) { 330*98d62e61SPatrick Bruenn printf("Verifing CCAT firmware failed, signature not found\n"); 331*98d62e61SPatrick Bruenn return FPGA_FAIL; 332*98d62e61SPatrick Bruenn } 333*98d62e61SPatrick Bruenn 334*98d62e61SPatrick Bruenn /* signal "CX booting OS" */ 335*98d62e61SPatrick Bruenn gpio_set_value(GPIO_LED_PWR_R, 1); 336*98d62e61SPatrick Bruenn gpio_set_value(GPIO_LED_PWR_G, 1); 337*98d62e61SPatrick Bruenn gpio_set_value(GPIO_LED_PWR_B, 0); 338*98d62e61SPatrick Bruenn return FPGA_SUCCESS; 339*98d62e61SPatrick Bruenn } 340*98d62e61SPatrick Bruenn 341*98d62e61SPatrick Bruenn static Altera_CYC2_Passive_Serial_fns ccat_fns = { 342*98d62e61SPatrick Bruenn .config = ccat_config_fn, 343*98d62e61SPatrick Bruenn .status = ccat_status_fn, 344*98d62e61SPatrick Bruenn .done = ccat_done_fn, 345*98d62e61SPatrick Bruenn .write = ccat_write_fn, 346*98d62e61SPatrick Bruenn .abort = ccat_post_fn, 347*98d62e61SPatrick Bruenn .post = ccat_post_fn, 348*98d62e61SPatrick Bruenn }; 349*98d62e61SPatrick Bruenn 350*98d62e61SPatrick Bruenn static Altera_desc ccat_fpga = { 351*98d62e61SPatrick Bruenn .family = Altera_CYC2, 352*98d62e61SPatrick Bruenn .iface = passive_serial, 353*98d62e61SPatrick Bruenn .size = CCAT_SIZE, 354*98d62e61SPatrick Bruenn .iface_fns = &ccat_fns, 355*98d62e61SPatrick Bruenn .base = CCAT_BASE_ADDR, 356*98d62e61SPatrick Bruenn }; 357*98d62e61SPatrick Bruenn 358*98d62e61SPatrick Bruenn int board_late_init(void) 359*98d62e61SPatrick Bruenn { 360*98d62e61SPatrick Bruenn if (!power_init()) 361*98d62e61SPatrick Bruenn clock_1GHz(); 362*98d62e61SPatrick Bruenn 363*98d62e61SPatrick Bruenn fpga_init(); 364*98d62e61SPatrick Bruenn fpga_add(fpga_altera, &ccat_fpga); 365*98d62e61SPatrick Bruenn 366*98d62e61SPatrick Bruenn return 0; 367*98d62e61SPatrick Bruenn } 368