198d62e61SPatrick Bruenn /* 298d62e61SPatrick Bruenn * Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG 398d62e61SPatrick Bruenn * Patrick Bruenn <p.bruenn@beckhoff.com> 498d62e61SPatrick Bruenn * 598d62e61SPatrick Bruenn * Based on <u-boot>/board/freescale/mx53loco/mx53loco.c 698d62e61SPatrick Bruenn * Copyright (C) 2011 Freescale Semiconductor, Inc. 798d62e61SPatrick Bruenn * 898d62e61SPatrick Bruenn * SPDX-License-Identifier: GPL-2.0+ 998d62e61SPatrick Bruenn */ 1098d62e61SPatrick Bruenn 1198d62e61SPatrick Bruenn #include <common.h> 129d922450SSimon Glass #include <dm.h> 1398d62e61SPatrick Bruenn #include <asm/io.h> 1498d62e61SPatrick Bruenn #include <asm/arch/imx-regs.h> 1598d62e61SPatrick Bruenn #include <asm/arch/sys_proto.h> 1698d62e61SPatrick Bruenn #include <asm/arch/crm_regs.h> 1798d62e61SPatrick Bruenn #include <asm/arch/clock.h> 1898d62e61SPatrick Bruenn #include <asm/arch/iomux-mx53.h> 1998d62e61SPatrick Bruenn #include <asm/arch/clock.h> 20*552a848eSStefano Babic #include <asm/mach-imx/mx5_video.h> 2198d62e61SPatrick Bruenn #include <ACEX1K.h> 2298d62e61SPatrick Bruenn #include <netdev.h> 2398d62e61SPatrick Bruenn #include <i2c.h> 2498d62e61SPatrick Bruenn #include <mmc.h> 2598d62e61SPatrick Bruenn #include <fsl_esdhc.h> 2698d62e61SPatrick Bruenn #include <asm/gpio.h> 2798d62e61SPatrick Bruenn #include <linux/fb.h> 2898d62e61SPatrick Bruenn #include <ipu_pixfmt.h> 2998d62e61SPatrick Bruenn #include <fs.h> 3098d62e61SPatrick Bruenn #include <dm/platform_data/serial_mxc.h> 3198d62e61SPatrick Bruenn 3298d62e61SPatrick Bruenn enum LED_GPIOS { 3398d62e61SPatrick Bruenn GPIO_SD1_CD = IMX_GPIO_NR(1, 1), 3498d62e61SPatrick Bruenn GPIO_SD2_CD = IMX_GPIO_NR(1, 4), 3598d62e61SPatrick Bruenn GPIO_LED_SD2_R = IMX_GPIO_NR(3, 16), 3698d62e61SPatrick Bruenn GPIO_LED_SD2_B = IMX_GPIO_NR(3, 17), 3798d62e61SPatrick Bruenn GPIO_LED_SD2_G = IMX_GPIO_NR(3, 18), 3898d62e61SPatrick Bruenn GPIO_LED_SD1_R = IMX_GPIO_NR(3, 19), 3998d62e61SPatrick Bruenn GPIO_LED_SD1_B = IMX_GPIO_NR(3, 20), 4098d62e61SPatrick Bruenn GPIO_LED_SD1_G = IMX_GPIO_NR(3, 21), 4198d62e61SPatrick Bruenn GPIO_LED_PWR_R = IMX_GPIO_NR(3, 22), 4298d62e61SPatrick Bruenn GPIO_LED_PWR_B = IMX_GPIO_NR(3, 23), 4398d62e61SPatrick Bruenn GPIO_LED_PWR_G = IMX_GPIO_NR(3, 24), 4498d62e61SPatrick Bruenn GPIO_SUPS_INT = IMX_GPIO_NR(3, 31), 4598d62e61SPatrick Bruenn GPIO_C3_CONFIG = IMX_GPIO_NR(6, 8), 4698d62e61SPatrick Bruenn GPIO_C3_STATUS = IMX_GPIO_NR(6, 7), 4798d62e61SPatrick Bruenn GPIO_C3_DONE = IMX_GPIO_NR(6, 9), 4898d62e61SPatrick Bruenn }; 4998d62e61SPatrick Bruenn 5098d62e61SPatrick Bruenn #define CCAT_BASE_ADDR ((void *)0xf0000000) 5198d62e61SPatrick Bruenn #define CCAT_END_ADDR (CCAT_BASE_ADDR + (1024 * 1024 * 32)) 5298d62e61SPatrick Bruenn #define CCAT_SIZE 1191788 5398d62e61SPatrick Bruenn #define CCAT_SIGN_ADDR (CCAT_BASE_ADDR + 12) 5498d62e61SPatrick Bruenn static const char CCAT_SIGNATURE[] = "CCAT"; 5598d62e61SPatrick Bruenn 5698d62e61SPatrick Bruenn static const u32 CCAT_MODE_CONFIG = 0x0024DC81; 5798d62e61SPatrick Bruenn static const u32 CCAT_MODE_RUN = 0x0033DC8F; 5898d62e61SPatrick Bruenn 5998d62e61SPatrick Bruenn DECLARE_GLOBAL_DATA_PTR; 6098d62e61SPatrick Bruenn 6198d62e61SPatrick Bruenn static uint32_t mx53_dram_size[2]; 6298d62e61SPatrick Bruenn 6398d62e61SPatrick Bruenn phys_size_t get_effective_memsize(void) 6498d62e61SPatrick Bruenn { 6598d62e61SPatrick Bruenn /* 6698d62e61SPatrick Bruenn * WARNING: We must override get_effective_memsize() function here 6798d62e61SPatrick Bruenn * to report only the size of the first DRAM bank. This is to make 6898d62e61SPatrick Bruenn * U-Boot relocator place U-Boot into valid memory, that is, at the 6998d62e61SPatrick Bruenn * end of the first DRAM bank. If we did not override this function 7098d62e61SPatrick Bruenn * like so, U-Boot would be placed at the address of the first DRAM 7198d62e61SPatrick Bruenn * bank + total DRAM size - sizeof(uboot), which in the setup where 7298d62e61SPatrick Bruenn * each DRAM bank contains 512MiB of DRAM would result in placing 7398d62e61SPatrick Bruenn * U-Boot into invalid memory area close to the end of the first 7498d62e61SPatrick Bruenn * DRAM bank. 7598d62e61SPatrick Bruenn */ 7698d62e61SPatrick Bruenn return mx53_dram_size[0]; 7798d62e61SPatrick Bruenn } 7898d62e61SPatrick Bruenn 7998d62e61SPatrick Bruenn int dram_init(void) 8098d62e61SPatrick Bruenn { 8198d62e61SPatrick Bruenn mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30); 8298d62e61SPatrick Bruenn mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30); 8398d62e61SPatrick Bruenn 8498d62e61SPatrick Bruenn gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1]; 8598d62e61SPatrick Bruenn 8698d62e61SPatrick Bruenn return 0; 8798d62e61SPatrick Bruenn } 8898d62e61SPatrick Bruenn 8976b00acaSSimon Glass int dram_init_banksize(void) 9098d62e61SPatrick Bruenn { 9198d62e61SPatrick Bruenn gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 9298d62e61SPatrick Bruenn gd->bd->bi_dram[0].size = mx53_dram_size[0]; 9398d62e61SPatrick Bruenn 9498d62e61SPatrick Bruenn gd->bd->bi_dram[1].start = PHYS_SDRAM_2; 9598d62e61SPatrick Bruenn gd->bd->bi_dram[1].size = mx53_dram_size[1]; 9676b00acaSSimon Glass 9776b00acaSSimon Glass return 0; 9898d62e61SPatrick Bruenn } 9998d62e61SPatrick Bruenn 10098d62e61SPatrick Bruenn u32 get_board_rev(void) 10198d62e61SPatrick Bruenn { 10298d62e61SPatrick Bruenn struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; 10398d62e61SPatrick Bruenn struct fuse_bank *bank = &iim->bank[0]; 10498d62e61SPatrick Bruenn struct fuse_bank0_regs *fuse = 10598d62e61SPatrick Bruenn (struct fuse_bank0_regs *)bank->fuse_regs; 10698d62e61SPatrick Bruenn 10798d62e61SPatrick Bruenn int rev = readl(&fuse->gp[6]); 10898d62e61SPatrick Bruenn 10998d62e61SPatrick Bruenn return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; 11098d62e61SPatrick Bruenn } 11198d62e61SPatrick Bruenn 11298d62e61SPatrick Bruenn /* 11398d62e61SPatrick Bruenn * Set CCAT mode 11498d62e61SPatrick Bruenn * @mode: use CCAT_MODE_CONFIG or CCAT_MODE_RUN 11598d62e61SPatrick Bruenn */ 11698d62e61SPatrick Bruenn void weim_cs0_settings(u32 mode) 11798d62e61SPatrick Bruenn { 11898d62e61SPatrick Bruenn struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR; 11998d62e61SPatrick Bruenn 12098d62e61SPatrick Bruenn writel(0x0, &weim_regs->cs0gcr1); 12198d62e61SPatrick Bruenn writel(mode, &weim_regs->cs0gcr1); 12298d62e61SPatrick Bruenn writel(0x00001002, &weim_regs->cs0gcr2); 12398d62e61SPatrick Bruenn 12498d62e61SPatrick Bruenn writel(0x04000000, &weim_regs->cs0rcr1); 12598d62e61SPatrick Bruenn writel(0x00000000, &weim_regs->cs0rcr2); 12698d62e61SPatrick Bruenn 12798d62e61SPatrick Bruenn writel(0x04000000, &weim_regs->cs0wcr1); 12898d62e61SPatrick Bruenn writel(0x00000000, &weim_regs->cs0wcr2); 12998d62e61SPatrick Bruenn } 13098d62e61SPatrick Bruenn 13198d62e61SPatrick Bruenn static void setup_gpio_eim(void) 13298d62e61SPatrick Bruenn { 13398d62e61SPatrick Bruenn gpio_direction_input(GPIO_C3_STATUS); 13498d62e61SPatrick Bruenn gpio_direction_input(GPIO_C3_DONE); 13598d62e61SPatrick Bruenn gpio_direction_output(GPIO_C3_CONFIG, 1); 13698d62e61SPatrick Bruenn 13798d62e61SPatrick Bruenn weim_cs0_settings(CCAT_MODE_RUN); 13898d62e61SPatrick Bruenn } 13998d62e61SPatrick Bruenn 14098d62e61SPatrick Bruenn static void setup_gpio_sups(void) 14198d62e61SPatrick Bruenn { 14298d62e61SPatrick Bruenn gpio_direction_input(GPIO_SUPS_INT); 14398d62e61SPatrick Bruenn 14498d62e61SPatrick Bruenn static const int BLINK_INTERVALL = 50000; 14598d62e61SPatrick Bruenn int status = 1; 14698d62e61SPatrick Bruenn while (gpio_get_value(GPIO_SUPS_INT)) { 14798d62e61SPatrick Bruenn /* signal "CX SUPS power fail" */ 14898d62e61SPatrick Bruenn gpio_set_value(GPIO_LED_PWR_R, 14998d62e61SPatrick Bruenn (++status / BLINK_INTERVALL) % 2); 15098d62e61SPatrick Bruenn } 15198d62e61SPatrick Bruenn 15298d62e61SPatrick Bruenn /* signal "CX power up" */ 15398d62e61SPatrick Bruenn gpio_set_value(GPIO_LED_PWR_R, 1); 15498d62e61SPatrick Bruenn } 15598d62e61SPatrick Bruenn 15698d62e61SPatrick Bruenn static void setup_gpio_leds(void) 15798d62e61SPatrick Bruenn { 15898d62e61SPatrick Bruenn gpio_direction_output(GPIO_LED_SD2_R, 0); 15998d62e61SPatrick Bruenn gpio_direction_output(GPIO_LED_SD2_B, 0); 16098d62e61SPatrick Bruenn gpio_direction_output(GPIO_LED_SD2_G, 0); 16198d62e61SPatrick Bruenn gpio_direction_output(GPIO_LED_SD1_R, 0); 16298d62e61SPatrick Bruenn gpio_direction_output(GPIO_LED_SD1_B, 0); 16398d62e61SPatrick Bruenn gpio_direction_output(GPIO_LED_SD1_G, 0); 16498d62e61SPatrick Bruenn gpio_direction_output(GPIO_LED_PWR_R, 0); 16598d62e61SPatrick Bruenn gpio_direction_output(GPIO_LED_PWR_B, 0); 16698d62e61SPatrick Bruenn gpio_direction_output(GPIO_LED_PWR_G, 0); 16798d62e61SPatrick Bruenn } 16898d62e61SPatrick Bruenn 16998d62e61SPatrick Bruenn #ifdef CONFIG_USB_EHCI_MX5 17098d62e61SPatrick Bruenn int board_ehci_hcd_init(int port) 17198d62e61SPatrick Bruenn { 17298d62e61SPatrick Bruenn /* request VBUS power enable pin, GPIO7_8 */ 17398d62e61SPatrick Bruenn gpio_direction_output(IMX_GPIO_NR(7, 8), 1); 17498d62e61SPatrick Bruenn return 0; 17598d62e61SPatrick Bruenn } 17698d62e61SPatrick Bruenn #endif 17798d62e61SPatrick Bruenn 17898d62e61SPatrick Bruenn #ifdef CONFIG_FSL_ESDHC 17998d62e61SPatrick Bruenn struct fsl_esdhc_cfg esdhc_cfg[2] = { 18098d62e61SPatrick Bruenn {MMC_SDHC1_BASE_ADDR}, 18198d62e61SPatrick Bruenn {MMC_SDHC2_BASE_ADDR}, 18298d62e61SPatrick Bruenn }; 18398d62e61SPatrick Bruenn 18498d62e61SPatrick Bruenn int board_mmc_getcd(struct mmc *mmc) 18598d62e61SPatrick Bruenn { 18698d62e61SPatrick Bruenn struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 18798d62e61SPatrick Bruenn int ret; 18898d62e61SPatrick Bruenn 18998d62e61SPatrick Bruenn gpio_direction_input(GPIO_SD1_CD); 19098d62e61SPatrick Bruenn gpio_direction_input(GPIO_SD2_CD); 19198d62e61SPatrick Bruenn 19298d62e61SPatrick Bruenn if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) 19398d62e61SPatrick Bruenn ret = !gpio_get_value(GPIO_SD1_CD); 19498d62e61SPatrick Bruenn else 19598d62e61SPatrick Bruenn ret = !gpio_get_value(GPIO_SD2_CD); 19698d62e61SPatrick Bruenn 19798d62e61SPatrick Bruenn return ret; 19898d62e61SPatrick Bruenn } 19998d62e61SPatrick Bruenn 20098d62e61SPatrick Bruenn int board_mmc_init(bd_t *bis) 20198d62e61SPatrick Bruenn { 20298d62e61SPatrick Bruenn u32 index; 20398d62e61SPatrick Bruenn int ret; 20498d62e61SPatrick Bruenn 20598d62e61SPatrick Bruenn esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 20698d62e61SPatrick Bruenn esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 20798d62e61SPatrick Bruenn 20898d62e61SPatrick Bruenn for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { 20998d62e61SPatrick Bruenn switch (index) { 21098d62e61SPatrick Bruenn case 0: 21198d62e61SPatrick Bruenn break; 21298d62e61SPatrick Bruenn case 1: 21398d62e61SPatrick Bruenn break; 21498d62e61SPatrick Bruenn default: 21598d62e61SPatrick Bruenn printf("Warning: you configured more ESDHC controller(%d) as supported by the board(2)\n", 21698d62e61SPatrick Bruenn CONFIG_SYS_FSL_ESDHC_NUM); 21798d62e61SPatrick Bruenn return -EINVAL; 21898d62e61SPatrick Bruenn } 21998d62e61SPatrick Bruenn ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]); 22098d62e61SPatrick Bruenn if (ret) 22198d62e61SPatrick Bruenn return ret; 22298d62e61SPatrick Bruenn } 22398d62e61SPatrick Bruenn 22498d62e61SPatrick Bruenn return 0; 22598d62e61SPatrick Bruenn } 22698d62e61SPatrick Bruenn #endif 22798d62e61SPatrick Bruenn 22898d62e61SPatrick Bruenn static int power_init(void) 22998d62e61SPatrick Bruenn { 23098d62e61SPatrick Bruenn /* nothing to do on CX9020 */ 23198d62e61SPatrick Bruenn return 0; 23298d62e61SPatrick Bruenn } 23398d62e61SPatrick Bruenn 23498d62e61SPatrick Bruenn static void clock_1GHz(void) 23598d62e61SPatrick Bruenn { 23698d62e61SPatrick Bruenn int ret; 23798d62e61SPatrick Bruenn u32 ref_clk = MXC_HCLK; 23898d62e61SPatrick Bruenn /* 23998d62e61SPatrick Bruenn * After increasing voltage to 1.25V, we can switch 24098d62e61SPatrick Bruenn * CPU clock to 1GHz and DDR to 400MHz safely 24198d62e61SPatrick Bruenn */ 24298d62e61SPatrick Bruenn ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK); 24398d62e61SPatrick Bruenn if (ret) 24498d62e61SPatrick Bruenn printf("CPU: Switch CPU clock to 1GHZ failed\n"); 24598d62e61SPatrick Bruenn 24698d62e61SPatrick Bruenn ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); 24798d62e61SPatrick Bruenn ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK); 24898d62e61SPatrick Bruenn if (ret) 24998d62e61SPatrick Bruenn printf("CPU: Switch DDR clock to 400MHz failed\n"); 25098d62e61SPatrick Bruenn } 25198d62e61SPatrick Bruenn 25298d62e61SPatrick Bruenn int board_early_init_f(void) 25398d62e61SPatrick Bruenn { 25498d62e61SPatrick Bruenn setup_gpio_leds(); 25598d62e61SPatrick Bruenn setup_gpio_sups(); 25698d62e61SPatrick Bruenn setup_gpio_eim(); 25798d62e61SPatrick Bruenn setup_iomux_lcd(); 25898d62e61SPatrick Bruenn 25998d62e61SPatrick Bruenn return 0; 26098d62e61SPatrick Bruenn } 26198d62e61SPatrick Bruenn 26298d62e61SPatrick Bruenn /* 26398d62e61SPatrick Bruenn * Do not overwrite the console 26498d62e61SPatrick Bruenn * Use always serial for U-Boot console 26598d62e61SPatrick Bruenn */ 26698d62e61SPatrick Bruenn int overwrite_console(void) 26798d62e61SPatrick Bruenn { 26898d62e61SPatrick Bruenn return 1; 26998d62e61SPatrick Bruenn } 27098d62e61SPatrick Bruenn 27198d62e61SPatrick Bruenn int board_init(void) 27298d62e61SPatrick Bruenn { 27398d62e61SPatrick Bruenn gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 27498d62e61SPatrick Bruenn 27598d62e61SPatrick Bruenn mxc_set_sata_internal_clock(); 27698d62e61SPatrick Bruenn 27798d62e61SPatrick Bruenn return 0; 27898d62e61SPatrick Bruenn } 27998d62e61SPatrick Bruenn 28098d62e61SPatrick Bruenn int checkboard(void) 28198d62e61SPatrick Bruenn { 28298d62e61SPatrick Bruenn puts("Board: Beckhoff CX9020\n"); 28398d62e61SPatrick Bruenn 28498d62e61SPatrick Bruenn return 0; 28598d62e61SPatrick Bruenn } 28698d62e61SPatrick Bruenn 28798d62e61SPatrick Bruenn static int ccat_config_fn(int assert_config, int flush, int cookie) 28898d62e61SPatrick Bruenn { 28998d62e61SPatrick Bruenn /* prepare FPGA for programming */ 29098d62e61SPatrick Bruenn weim_cs0_settings(CCAT_MODE_CONFIG); 29198d62e61SPatrick Bruenn gpio_set_value(GPIO_C3_CONFIG, 0); 29298d62e61SPatrick Bruenn udelay(1); 29398d62e61SPatrick Bruenn gpio_set_value(GPIO_C3_CONFIG, 1); 29498d62e61SPatrick Bruenn udelay(230); 29598d62e61SPatrick Bruenn 29698d62e61SPatrick Bruenn return FPGA_SUCCESS; 29798d62e61SPatrick Bruenn } 29898d62e61SPatrick Bruenn 29998d62e61SPatrick Bruenn static int ccat_status_fn(int cookie) 30098d62e61SPatrick Bruenn { 30198d62e61SPatrick Bruenn return FPGA_FAIL; 30298d62e61SPatrick Bruenn } 30398d62e61SPatrick Bruenn 30498d62e61SPatrick Bruenn static int ccat_write_fn(const void *buf, size_t buf_len, int flush, int cookie) 30598d62e61SPatrick Bruenn { 30698d62e61SPatrick Bruenn const uint8_t *const buffer = buf; 30798d62e61SPatrick Bruenn 30898d62e61SPatrick Bruenn /* program CCAT */ 30998d62e61SPatrick Bruenn int i; 31098d62e61SPatrick Bruenn for (i = 0; i < buf_len; ++i) 31198d62e61SPatrick Bruenn writeb(buffer[i], CCAT_BASE_ADDR); 31298d62e61SPatrick Bruenn 31398d62e61SPatrick Bruenn writeb(0xff, CCAT_BASE_ADDR); 31498d62e61SPatrick Bruenn writeb(0xff, CCAT_BASE_ADDR); 31598d62e61SPatrick Bruenn 31698d62e61SPatrick Bruenn return FPGA_SUCCESS; 31798d62e61SPatrick Bruenn } 31898d62e61SPatrick Bruenn 31998d62e61SPatrick Bruenn static int ccat_done_fn(int cookie) 32098d62e61SPatrick Bruenn { 32198d62e61SPatrick Bruenn /* programming complete? */ 32298d62e61SPatrick Bruenn return gpio_get_value(GPIO_C3_DONE); 32398d62e61SPatrick Bruenn } 32498d62e61SPatrick Bruenn 32598d62e61SPatrick Bruenn static int ccat_post_fn(int cookie) 32698d62e61SPatrick Bruenn { 32798d62e61SPatrick Bruenn /* switch to FPGA run mode */ 32898d62e61SPatrick Bruenn weim_cs0_settings(CCAT_MODE_RUN); 32998d62e61SPatrick Bruenn invalidate_dcache_range((ulong) CCAT_BASE_ADDR, (ulong) CCAT_END_ADDR); 33098d62e61SPatrick Bruenn 33198d62e61SPatrick Bruenn if (memcmp(CCAT_SIGN_ADDR, CCAT_SIGNATURE, sizeof(CCAT_SIGNATURE))) { 33298d62e61SPatrick Bruenn printf("Verifing CCAT firmware failed, signature not found\n"); 33398d62e61SPatrick Bruenn return FPGA_FAIL; 33498d62e61SPatrick Bruenn } 33598d62e61SPatrick Bruenn 33698d62e61SPatrick Bruenn /* signal "CX booting OS" */ 33798d62e61SPatrick Bruenn gpio_set_value(GPIO_LED_PWR_R, 1); 33898d62e61SPatrick Bruenn gpio_set_value(GPIO_LED_PWR_G, 1); 33998d62e61SPatrick Bruenn gpio_set_value(GPIO_LED_PWR_B, 0); 34098d62e61SPatrick Bruenn return FPGA_SUCCESS; 34198d62e61SPatrick Bruenn } 34298d62e61SPatrick Bruenn 34398d62e61SPatrick Bruenn static Altera_CYC2_Passive_Serial_fns ccat_fns = { 34498d62e61SPatrick Bruenn .config = ccat_config_fn, 34598d62e61SPatrick Bruenn .status = ccat_status_fn, 34698d62e61SPatrick Bruenn .done = ccat_done_fn, 34798d62e61SPatrick Bruenn .write = ccat_write_fn, 34898d62e61SPatrick Bruenn .abort = ccat_post_fn, 34998d62e61SPatrick Bruenn .post = ccat_post_fn, 35098d62e61SPatrick Bruenn }; 35198d62e61SPatrick Bruenn 35298d62e61SPatrick Bruenn static Altera_desc ccat_fpga = { 35398d62e61SPatrick Bruenn .family = Altera_CYC2, 35498d62e61SPatrick Bruenn .iface = passive_serial, 35598d62e61SPatrick Bruenn .size = CCAT_SIZE, 35698d62e61SPatrick Bruenn .iface_fns = &ccat_fns, 35798d62e61SPatrick Bruenn .base = CCAT_BASE_ADDR, 35898d62e61SPatrick Bruenn }; 35998d62e61SPatrick Bruenn 36098d62e61SPatrick Bruenn int board_late_init(void) 36198d62e61SPatrick Bruenn { 36298d62e61SPatrick Bruenn if (!power_init()) 36398d62e61SPatrick Bruenn clock_1GHz(); 36498d62e61SPatrick Bruenn 36598d62e61SPatrick Bruenn fpga_init(); 36698d62e61SPatrick Bruenn fpga_add(fpga_altera, &ccat_fpga); 36798d62e61SPatrick Bruenn 36898d62e61SPatrick Bruenn return 0; 36998d62e61SPatrick Bruenn } 370