1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2013 Stefan Roese <sr@denx.de> 4 */ 5 6 #include <common.h> 7 #include <asm/io.h> 8 #include <asm/arch/clock.h> 9 #include <asm/arch/imx-regs.h> 10 #include <asm/arch/iomux.h> 11 #include <asm/arch/mx6-pins.h> 12 #include <asm/arch/crm_regs.h> 13 #include <asm/arch/sys_proto.h> 14 #include <asm/gpio.h> 15 #include <asm/mach-imx/iomux-v3.h> 16 #include <asm/mach-imx/mxc_i2c.h> 17 #include <asm/mach-imx/boot_mode.h> 18 #include <mmc.h> 19 #include <fsl_esdhc.h> 20 #include <micrel.h> 21 #include <miiphy.h> 22 #include <netdev.h> 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 27 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 28 29 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ 30 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 31 32 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 33 PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 34 35 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 36 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 37 PAD_CTL_ODE | PAD_CTL_SRE_FAST) 38 39 int dram_init(void) 40 { 41 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); 42 43 return 0; 44 } 45 46 iomux_v3_cfg_t const uart1_pads[] = { 47 MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 48 MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 49 }; 50 51 iomux_v3_cfg_t const uart2_pads[] = { 52 MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 53 MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 54 }; 55 56 iomux_v3_cfg_t const uart4_pads[] = { 57 MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 58 MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 59 }; 60 61 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 62 63 struct i2c_pads_info i2c_pad_info0 = { 64 .scl = { 65 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC, 66 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC, 67 .gp = IMX_GPIO_NR(5, 27) 68 }, 69 .sda = { 70 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC, 71 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC, 72 .gp = IMX_GPIO_NR(5, 26) 73 } 74 }; 75 76 struct i2c_pads_info i2c_pad_info2 = { 77 .scl = { 78 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC, 79 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC, 80 .gp = IMX_GPIO_NR(1, 3) 81 }, 82 .sda = { 83 .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC, 84 .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC, 85 .gp = IMX_GPIO_NR(7, 11) 86 } 87 }; 88 89 iomux_v3_cfg_t const usdhc3_pads[] = { 90 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 91 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 92 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 93 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 94 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 95 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 96 MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 97 }; 98 99 iomux_v3_cfg_t const enet_pads1[] = { 100 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 101 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 102 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 103 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 104 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 105 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 106 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 107 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 108 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 109 /* pin 35 - 1 (PHY_AD2) on reset */ 110 MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), 111 /* pin 32 - 1 - (MODE0) all */ 112 MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), 113 /* pin 31 - 1 - (MODE1) all */ 114 MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), 115 /* pin 28 - 1 - (MODE2) all */ 116 MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), 117 /* pin 27 - 1 - (MODE3) all */ 118 MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), 119 /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ 120 MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL), 121 /* pin 42 PHY nRST */ 122 MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), 123 }; 124 125 iomux_v3_cfg_t const enet_pads2[] = { 126 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 127 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 128 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 129 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 130 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 131 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 132 }; 133 134 iomux_v3_cfg_t nfc_pads[] = { 135 MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), 136 MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), 137 MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL), 138 MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL), 139 MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL), 140 MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL), 141 MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL), 142 MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL), 143 MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL), 144 MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL), 145 MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL), 146 MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL), 147 MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL), 148 MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL), 149 MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL), 150 MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL), 151 MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL), 152 MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL), 153 MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL), 154 }; 155 156 static void setup_gpmi_nand(void) 157 { 158 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 159 160 /* config gpmi nand iomux */ 161 imx_iomux_v3_setup_multiple_pads(nfc_pads, 162 ARRAY_SIZE(nfc_pads)); 163 164 /* config gpmi and bch clock to 100 MHz */ 165 clrsetbits_le32(&mxc_ccm->cs2cdr, 166 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | 167 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | 168 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, 169 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | 170 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | 171 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); 172 173 /* enable gpmi and bch clock gating */ 174 setbits_le32(&mxc_ccm->CCGR4, 175 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | 176 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | 177 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | 178 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | 179 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); 180 181 /* enable apbh clock gating */ 182 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); 183 } 184 185 static void setup_iomux_enet(void) 186 { 187 gpio_direction_output(IMX_GPIO_NR(3, 23), 0); 188 gpio_direction_output(IMX_GPIO_NR(6, 30), 1); 189 gpio_direction_output(IMX_GPIO_NR(6, 25), 1); 190 gpio_direction_output(IMX_GPIO_NR(6, 27), 1); 191 gpio_direction_output(IMX_GPIO_NR(6, 28), 1); 192 gpio_direction_output(IMX_GPIO_NR(6, 29), 1); 193 imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); 194 gpio_direction_output(IMX_GPIO_NR(6, 24), 1); 195 196 /* Need delay 10ms according to KSZ9021 spec */ 197 udelay(1000 * 10); 198 gpio_set_value(IMX_GPIO_NR(3, 23), 1); 199 200 imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); 201 } 202 203 static void setup_iomux_uart(void) 204 { 205 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 206 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); 207 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); 208 } 209 210 #ifdef CONFIG_USB_EHCI_MX6 211 int board_ehci_hcd_init(int port) 212 { 213 return 0; 214 } 215 216 #endif 217 218 #ifdef CONFIG_FSL_ESDHC 219 struct fsl_esdhc_cfg usdhc_cfg[1] = { 220 { USDHC3_BASE_ADDR }, 221 }; 222 223 int board_mmc_getcd(struct mmc *mmc) 224 { 225 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 226 227 if (cfg->esdhc_base == USDHC3_BASE_ADDR) { 228 gpio_direction_input(IMX_GPIO_NR(7, 0)); 229 return !gpio_get_value(IMX_GPIO_NR(7, 0)); 230 } 231 232 return 0; 233 } 234 235 int board_mmc_init(bd_t *bis) 236 { 237 /* 238 * Only one USDHC controller on titianium 239 */ 240 imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 241 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 242 243 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); 244 } 245 #endif 246 247 int board_phy_config(struct phy_device *phydev) 248 { 249 /* min rx data delay */ 250 ksz9021_phy_extended_write(phydev, 251 MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0); 252 /* min tx data delay */ 253 ksz9021_phy_extended_write(phydev, 254 MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0); 255 /* max rx/tx clock delay, min rx/tx control */ 256 ksz9021_phy_extended_write(phydev, 257 MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0); 258 if (phydev->drv->config) 259 phydev->drv->config(phydev); 260 261 return 0; 262 } 263 264 int board_eth_init(bd_t *bis) 265 { 266 setup_iomux_enet(); 267 268 return cpu_eth_init(bis); 269 } 270 271 int board_early_init_f(void) 272 { 273 setup_iomux_uart(); 274 275 return 0; 276 } 277 278 int board_init(void) 279 { 280 /* address of boot parameters */ 281 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 282 283 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); 284 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); 285 286 setup_gpmi_nand(); 287 288 return 0; 289 } 290 291 int checkboard(void) 292 { 293 puts("Board: Titanium\n"); 294 295 return 0; 296 } 297 298 #ifdef CONFIG_CMD_BMODE 299 static const struct boot_mode board_boot_modes[] = { 300 /* NAND */ 301 { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) }, 302 /* 4 bit bus width */ 303 { "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) }, 304 { "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) }, 305 { NULL, 0 }, 306 }; 307 #endif 308 309 int misc_init_r(void) 310 { 311 #ifdef CONFIG_CMD_BMODE 312 add_board_boot_modes(board_boot_modes); 313 #endif 314 315 return 0; 316 } 317