1 /* 2 * Copyright (C) 2013 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <asm/arch/clock.h> 10 #include <asm/arch/imx-regs.h> 11 #include <asm/arch/iomux.h> 12 #include <asm/arch/mx6-pins.h> 13 #include <asm/arch/crm_regs.h> 14 #include <asm/arch/sys_proto.h> 15 #include <asm/gpio.h> 16 #include <asm/imx-common/iomux-v3.h> 17 #include <asm/imx-common/mxc_i2c.h> 18 #include <asm/imx-common/boot_mode.h> 19 #include <mmc.h> 20 #include <fsl_esdhc.h> 21 #include <micrel.h> 22 #include <miiphy.h> 23 #include <netdev.h> 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 28 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 29 30 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ 31 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 32 33 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 34 PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 35 36 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 37 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 38 PAD_CTL_ODE | PAD_CTL_SRE_FAST) 39 40 int dram_init(void) 41 { 42 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); 43 44 return 0; 45 } 46 47 iomux_v3_cfg_t const uart1_pads[] = { 48 MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 49 MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 50 }; 51 52 iomux_v3_cfg_t const uart2_pads[] = { 53 MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 54 MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 55 }; 56 57 iomux_v3_cfg_t const uart4_pads[] = { 58 MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 59 MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 60 }; 61 62 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 63 64 struct i2c_pads_info i2c_pad_info0 = { 65 .scl = { 66 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC, 67 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC, 68 .gp = IMX_GPIO_NR(5, 27) 69 }, 70 .sda = { 71 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC, 72 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC, 73 .gp = IMX_GPIO_NR(5, 26) 74 } 75 }; 76 77 struct i2c_pads_info i2c_pad_info2 = { 78 .scl = { 79 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC, 80 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC, 81 .gp = IMX_GPIO_NR(1, 3) 82 }, 83 .sda = { 84 .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC, 85 .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC, 86 .gp = IMX_GPIO_NR(7, 11) 87 } 88 }; 89 90 iomux_v3_cfg_t const usdhc3_pads[] = { 91 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 92 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 93 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 94 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 95 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 96 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 97 MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 98 }; 99 100 iomux_v3_cfg_t const enet_pads1[] = { 101 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 102 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 103 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 104 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 105 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 106 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 107 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 108 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 109 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 110 /* pin 35 - 1 (PHY_AD2) on reset */ 111 MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), 112 /* pin 32 - 1 - (MODE0) all */ 113 MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), 114 /* pin 31 - 1 - (MODE1) all */ 115 MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), 116 /* pin 28 - 1 - (MODE2) all */ 117 MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), 118 /* pin 27 - 1 - (MODE3) all */ 119 MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), 120 /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ 121 MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL), 122 /* pin 42 PHY nRST */ 123 MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), 124 }; 125 126 iomux_v3_cfg_t const enet_pads2[] = { 127 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 128 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 129 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 130 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 131 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 132 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 133 }; 134 135 iomux_v3_cfg_t nfc_pads[] = { 136 MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), 137 MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), 138 MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL), 139 MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL), 140 MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL), 141 MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL), 142 MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL), 143 MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL), 144 MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL), 145 MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL), 146 MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL), 147 MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL), 148 MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL), 149 MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL), 150 MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL), 151 MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL), 152 MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL), 153 MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL), 154 MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL), 155 }; 156 157 static void setup_gpmi_nand(void) 158 { 159 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 160 161 /* config gpmi nand iomux */ 162 imx_iomux_v3_setup_multiple_pads(nfc_pads, 163 ARRAY_SIZE(nfc_pads)); 164 165 /* config gpmi and bch clock to 100 MHz */ 166 clrsetbits_le32(&mxc_ccm->cs2cdr, 167 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | 168 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | 169 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, 170 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | 171 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | 172 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); 173 174 /* enable gpmi and bch clock gating */ 175 setbits_le32(&mxc_ccm->CCGR4, 176 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | 177 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | 178 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | 179 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | 180 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); 181 182 /* enable apbh clock gating */ 183 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); 184 } 185 186 static void setup_iomux_enet(void) 187 { 188 gpio_direction_output(IMX_GPIO_NR(3, 23), 0); 189 gpio_direction_output(IMX_GPIO_NR(6, 30), 1); 190 gpio_direction_output(IMX_GPIO_NR(6, 25), 1); 191 gpio_direction_output(IMX_GPIO_NR(6, 27), 1); 192 gpio_direction_output(IMX_GPIO_NR(6, 28), 1); 193 gpio_direction_output(IMX_GPIO_NR(6, 29), 1); 194 imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); 195 gpio_direction_output(IMX_GPIO_NR(6, 24), 1); 196 197 /* Need delay 10ms according to KSZ9021 spec */ 198 udelay(1000 * 10); 199 gpio_set_value(IMX_GPIO_NR(3, 23), 1); 200 201 imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); 202 } 203 204 static void setup_iomux_uart(void) 205 { 206 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 207 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); 208 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); 209 } 210 211 #ifdef CONFIG_USB_EHCI_MX6 212 int board_ehci_hcd_init(int port) 213 { 214 return 0; 215 } 216 217 #endif 218 219 #ifdef CONFIG_FSL_ESDHC 220 struct fsl_esdhc_cfg usdhc_cfg[1] = { 221 { USDHC3_BASE_ADDR }, 222 }; 223 224 int board_mmc_getcd(struct mmc *mmc) 225 { 226 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 227 228 if (cfg->esdhc_base == USDHC3_BASE_ADDR) { 229 gpio_direction_input(IMX_GPIO_NR(7, 0)); 230 return !gpio_get_value(IMX_GPIO_NR(7, 0)); 231 } 232 233 return 0; 234 } 235 236 int board_mmc_init(bd_t *bis) 237 { 238 /* 239 * Only one USDHC controller on titianium 240 */ 241 imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 242 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 243 244 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); 245 } 246 #endif 247 248 int board_phy_config(struct phy_device *phydev) 249 { 250 /* min rx data delay */ 251 ksz9021_phy_extended_write(phydev, 252 MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0); 253 /* min tx data delay */ 254 ksz9021_phy_extended_write(phydev, 255 MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0); 256 /* max rx/tx clock delay, min rx/tx control */ 257 ksz9021_phy_extended_write(phydev, 258 MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0); 259 if (phydev->drv->config) 260 phydev->drv->config(phydev); 261 262 return 0; 263 } 264 265 int board_eth_init(bd_t *bis) 266 { 267 setup_iomux_enet(); 268 269 return cpu_eth_init(bis); 270 } 271 272 int board_early_init_f(void) 273 { 274 setup_iomux_uart(); 275 276 return 0; 277 } 278 279 int board_init(void) 280 { 281 /* address of boot parameters */ 282 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 283 284 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); 285 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); 286 287 setup_gpmi_nand(); 288 289 return 0; 290 } 291 292 int checkboard(void) 293 { 294 puts("Board: Titanium\n"); 295 296 return 0; 297 } 298 299 #ifdef CONFIG_CMD_BMODE 300 static const struct boot_mode board_boot_modes[] = { 301 /* NAND */ 302 { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) }, 303 /* 4 bit bus width */ 304 { "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) }, 305 { "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) }, 306 { NULL, 0 }, 307 }; 308 #endif 309 310 int misc_init_r(void) 311 { 312 #ifdef CONFIG_CMD_BMODE 313 add_board_boot_modes(board_boot_modes); 314 #endif 315 316 return 0; 317 } 318