1/* 2 * Projectiondesign AS 3 * Derived from ./board/freescale/mx6qsabrelite/imximage.cfg 4 * 5 * Copyright (C) 2011 Freescale Semiconductor, Inc. 6 * Jason Liu <r64343@freescale.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 * 10 * Refer doc/README.imximage for more details about how-to configure 11 * and create imximage boot image 12 * 13 * The syntax is taken as close as possible with the kwbimage 14 */ 15 16/* image version */ 17 18IMAGE_VERSION 2 19 20/* 21 * Boot Device : one of 22 * sd, nand 23 */ 24BOOT_FROM nand 25 26/* 27 * Device Configuration Data (DCD) 28 * 29 * Each entry must have the format: 30 * Addr-type Address Value 31 * 32 * where: 33 * Addr-type register length (1,2 or 4 bytes) 34 * Address absolute address of the register 35 * value value to be stored in the register 36 */ 37 38#define __ASSEMBLY__ 39#include <config.h> 40#include "asm/arch/mx6-ddr.h" 41#include "asm/arch/iomux.h" 42#include "asm/arch/crm_regs.h" 43 44DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 45DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 46DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 47DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 48DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 49DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 50DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 51DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 52 53DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 54DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 55DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 56DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 57DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 58DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 59DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 60DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 61 62DATA 4, MX6_IOM_DRAM_CAS, 0x00020030 63DATA 4, MX6_IOM_DRAM_RAS, 0x00020030 64DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 65DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 66 67DATA 4, MX6_IOM_DRAM_RESET, 0x00020030 68DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 69DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 70 71DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 72 73DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 74DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 75 76DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 77DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 78DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 79DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 80DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 81DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 82DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 83DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 84DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 85 86/* (differential input) */ 87DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 88/* disable ddr pullups */ 89DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 90/* (differential input) */ 91DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 92/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ 93DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 94/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ 95DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 96 97/* Read data DQ Byte0-3 delay */ 98DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 99DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 100DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 101DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 102DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 103DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 104DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 105DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 106 107/* 108 * MDMISC mirroring interleaved (row/bank/col) 109 */ 110DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 111 112DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 113DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7975 114DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF538E64 115DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB 116DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 117DATA 4, MX6_MMDC_P0_MDOR, 0x005B0E21 118DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 119DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 120DATA 4, MX6_MMDC_P0_MDASP, 0x00000017 121DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000 122DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 123DATA 4, MX6_MMDC_P0_MDSCR, 0x0408803A 124DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 125DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803B 126DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031 127DATA 4, MX6_MMDC_P0_MDSCR, 0x00428039 128DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030 129DATA 4, MX6_MMDC_P0_MDSCR, 0x09408038 130DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 131DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048 132DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003 133DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003 134DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 135DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 136DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 137DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x434B0350 138DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x034C0359 139DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x434B0350 140DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03650348 141DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4436383B 142DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x39393341 143DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x35373933 144DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x48254A36 145DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F 146DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F 147DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00440044 148DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00440044 149DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 150DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 151DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 152DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 153 154/* set the default clock gate to save power */ 155DATA 4, CCM_CCGR0, 0x00C03F3F 156DATA 4, CCM_CCGR1, 0x0030FC03 157DATA 4, CCM_CCGR2, 0x0FFFC000 158DATA 4, CCM_CCGR3, 0x3FF00000 159DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */ 160DATA 4, CCM_CCGR5, 0x0F0000C3 161DATA 4, CCM_CCGR6, 0x000003FF 162 163/* enable AXI cache for VDOA/VPU/IPU */ 164DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF 165/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ 166DATA 4, MX6_IOMUXC_GPR6, 0x007F007F 167DATA 4, MX6_IOMUXC_GPR7, 0x007F007F 168