1 /* 2 * Copyright (C) 2014 Stefan Roese <sr@denx.de> 3 * 4 * Based on: gw_ventana_spl.c which is: 5 * Copyright (C) 2014 Gateworks Corporation 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <i2c.h> 12 #include <asm/io.h> 13 #include <asm/arch/iomux.h> 14 #include <asm/arch/mx6-ddr.h> 15 #include <asm/arch/mx6-pins.h> 16 #include <asm/arch/sys_proto.h> 17 #include <asm/mach-imx/boot_mode.h> 18 #include <asm/mach-imx/iomux-v3.h> 19 #include <asm/mach-imx/mxc_i2c.h> 20 #include <spl.h> 21 22 #include "platinum.h" 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 #undef RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */ 27 28 /* Configure MX6Q/DUAL mmdc DDR io registers */ 29 struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { 30 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ 31 .dram_sdclk_0 = 0x00020030, 32 .dram_sdclk_1 = 0x00020030, 33 .dram_cas = 0x00020030, 34 .dram_ras = 0x00020030, 35 .dram_reset = 0x00020030, 36 /* SDCKE[0:1]: 100k pull-up */ 37 .dram_sdcke0 = 0x00003000, 38 .dram_sdcke1 = 0x00003000, 39 /* SDBA2: pull-up disabled */ 40 .dram_sdba2 = 0x00000000, 41 /* SDODT[0:1]: 100k pull-up, 40 ohm */ 42 .dram_sdodt0 = 0x00003030, 43 .dram_sdodt1 = 0x00003030, 44 /* SDQS[0:7]: Differential input, 40 ohm */ 45 .dram_sdqs0 = 0x00000030, 46 .dram_sdqs1 = 0x00000030, 47 .dram_sdqs2 = 0x00000030, 48 .dram_sdqs3 = 0x00000030, 49 .dram_sdqs4 = 0x00000030, 50 .dram_sdqs5 = 0x00000030, 51 .dram_sdqs6 = 0x00000030, 52 .dram_sdqs7 = 0x00000030, 53 /* DQM[0:7]: Differential input, 40 ohm */ 54 .dram_dqm0 = 0x00020030, 55 .dram_dqm1 = 0x00020030, 56 .dram_dqm2 = 0x00020030, 57 .dram_dqm3 = 0x00020030, 58 .dram_dqm4 = 0x00020030, 59 .dram_dqm5 = 0x00020030, 60 .dram_dqm6 = 0x00020030, 61 .dram_dqm7 = 0x00020030, 62 }; 63 64 /* Configure MX6Q/DUAL mmdc GRP io registers */ 65 struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { 66 /* DDR3 */ 67 .grp_ddr_type = 0x000c0000, 68 .grp_ddrmode_ctl = 0x00020000, 69 /* disable DDR pullups */ 70 .grp_ddrpke = 0x00000000, 71 /* ADDR[00:16], SDBA[0:1]: 40 ohm */ 72 .grp_addds = 0x00000030, 73 /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ 74 .grp_ctlds = 0x00000030, 75 /* DATA[00:63]: Differential input, 40 ohm */ 76 .grp_ddrmode = 0x00020000, 77 .grp_b0ds = 0x00000030, 78 .grp_b1ds = 0x00000030, 79 .grp_b2ds = 0x00000030, 80 .grp_b3ds = 0x00000030, 81 .grp_b4ds = 0x00000030, 82 .grp_b5ds = 0x00000030, 83 .grp_b6ds = 0x00000030, 84 .grp_b7ds = 0x00000030, 85 }; 86 87 /* MT41J128M16JT-125 */ 88 static struct mx6_ddr3_cfg mt41j128m16jt_125 = { 89 .mem_speed = 1600, 90 .density = 2, 91 .width = 16, 92 .banks = 8, 93 .rowaddr = 14, 94 .coladdr = 10, 95 .pagesz = 2, 96 .trcd = 1375, 97 .trcmin = 4875, 98 .trasmin = 3500, 99 }; 100 101 static struct mx6_mmdc_calibration mx6dq_mmdc_calib = { 102 /* Write leveling calibration determine */ 103 .p0_mpwldectrl0 = 0x001f001f, 104 .p0_mpwldectrl1 = 0x001f001f, 105 .p1_mpwldectrl0 = 0x00440044, 106 .p1_mpwldectrl1 = 0x00440044, 107 /* Read DQS Gating calibration */ 108 .p0_mpdgctrl0 = 0x434b0350, 109 .p0_mpdgctrl1 = 0x034c0359, 110 .p1_mpdgctrl0 = 0x434b0350, 111 .p1_mpdgctrl1 = 0x03650348, 112 /* Read Calibration: DQS delay relative to DQ read access */ 113 .p0_mprddlctl = 0x4436383b, 114 .p1_mprddlctl = 0x39393341, 115 /* Write Calibration: DQ/DM delay relative to DQS write access */ 116 .p0_mpwrdlctl = 0x35373933, 117 .p1_mpwrdlctl = 0x48254a36, 118 }; 119 120 static void spl_dram_init(int width) 121 { 122 struct mx6_ddr3_cfg *mem = &mt41j128m16jt_125; 123 struct mx6_ddr_sysinfo sysinfo = { 124 /* width of data bus:0=16,1=32,2=64 */ 125 .dsize = width / 32, 126 /* config for full 4GB range so that get_mem_size() works */ 127 .cs_density = 32, /* 32Gb per CS */ 128 /* single chip select */ 129 .ncs = 1, 130 .cs1_mirror = 1, 131 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ 132 #ifdef RTT_NOM_120OHM 133 .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ 134 #else 135 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ 136 #endif 137 .walat = 0, /* Write additional latency */ 138 .ralat = 5, /* Read additional latency */ 139 .mif3_mode = 3, /* Command prediction working mode */ 140 .bi_on = 1, /* Bank interleaving enabled */ 141 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 142 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 143 .ddr_type = DDR_TYPE_DDR3, 144 .refsel = 1, /* Refresh cycles at 32KHz */ 145 .refr = 7, /* 8 refresh commands per refresh cycle */ 146 }; 147 148 mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); 149 mx6_dram_cfg(&sysinfo, &mx6dq_mmdc_calib, mem); 150 } 151 152 /* 153 * Called from C runtime startup code (arch/arm/lib/crt0.S:_main) 154 * - we have a stack and a place to store GD, both in SRAM 155 * - no variable global data is available 156 */ 157 void board_init_f(ulong dummy) 158 { 159 /* Setup AIPS and disable watchdog */ 160 arch_cpu_init(); 161 162 ccgr_init(); 163 gpr_init(); 164 165 /* UART iomux */ 166 board_early_init_f(); 167 168 /* Setup GP timer */ 169 timer_init(); 170 171 /* UART clocks enabled and gd valid - init serial console */ 172 preloader_console_init(); 173 174 /* Init DDR with 32bit width */ 175 spl_dram_init(32); 176 177 /* Clear the BSS */ 178 memset(__bss_start, 0, __bss_end - __bss_start); 179 180 /* 181 * Setup enet related MUXing early to give the PHY 182 * some time to wake-up from reset 183 */ 184 platinum_setup_enet(); 185 186 /* load/boot image from boot device */ 187 board_init_r(NULL, 0); 188 } 189