1*5d6050fdSStefan Roese /* 2*5d6050fdSStefan Roese * Copyright (C) 2014 Stefan Roese <sr@denx.de> 3*5d6050fdSStefan Roese * 4*5d6050fdSStefan Roese * Based on: gw_ventana_spl.c which is: 5*5d6050fdSStefan Roese * Copyright (C) 2014 Gateworks Corporation 6*5d6050fdSStefan Roese * 7*5d6050fdSStefan Roese * SPDX-License-Identifier: GPL-2.0+ 8*5d6050fdSStefan Roese */ 9*5d6050fdSStefan Roese 10*5d6050fdSStefan Roese #include <common.h> 11*5d6050fdSStefan Roese #include <i2c.h> 12*5d6050fdSStefan Roese #include <asm/io.h> 13*5d6050fdSStefan Roese #include <asm/arch/iomux.h> 14*5d6050fdSStefan Roese #include <asm/arch/mx6-ddr.h> 15*5d6050fdSStefan Roese #include <asm/arch/mx6-pins.h> 16*5d6050fdSStefan Roese #include <asm/arch/sys_proto.h> 17*5d6050fdSStefan Roese #include <asm/imx-common/boot_mode.h> 18*5d6050fdSStefan Roese #include <asm/imx-common/iomux-v3.h> 19*5d6050fdSStefan Roese #include <asm/imx-common/mxc_i2c.h> 20*5d6050fdSStefan Roese #include <spl.h> 21*5d6050fdSStefan Roese 22*5d6050fdSStefan Roese #include "platinum.h" 23*5d6050fdSStefan Roese 24*5d6050fdSStefan Roese DECLARE_GLOBAL_DATA_PTR; 25*5d6050fdSStefan Roese 26*5d6050fdSStefan Roese #undef RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */ 27*5d6050fdSStefan Roese 28*5d6050fdSStefan Roese /* Configure MX6Q/DUAL mmdc DDR io registers */ 29*5d6050fdSStefan Roese struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { 30*5d6050fdSStefan Roese /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ 31*5d6050fdSStefan Roese .dram_sdclk_0 = 0x00020030, 32*5d6050fdSStefan Roese .dram_sdclk_1 = 0x00020030, 33*5d6050fdSStefan Roese .dram_cas = 0x00020030, 34*5d6050fdSStefan Roese .dram_ras = 0x00020030, 35*5d6050fdSStefan Roese .dram_reset = 0x00020030, 36*5d6050fdSStefan Roese /* SDCKE[0:1]: 100k pull-up */ 37*5d6050fdSStefan Roese .dram_sdcke0 = 0x00003000, 38*5d6050fdSStefan Roese .dram_sdcke1 = 0x00003000, 39*5d6050fdSStefan Roese /* SDBA2: pull-up disabled */ 40*5d6050fdSStefan Roese .dram_sdba2 = 0x00000000, 41*5d6050fdSStefan Roese /* SDODT[0:1]: 100k pull-up, 40 ohm */ 42*5d6050fdSStefan Roese .dram_sdodt0 = 0x00003030, 43*5d6050fdSStefan Roese .dram_sdodt1 = 0x00003030, 44*5d6050fdSStefan Roese /* SDQS[0:7]: Differential input, 40 ohm */ 45*5d6050fdSStefan Roese .dram_sdqs0 = 0x00000030, 46*5d6050fdSStefan Roese .dram_sdqs1 = 0x00000030, 47*5d6050fdSStefan Roese .dram_sdqs2 = 0x00000030, 48*5d6050fdSStefan Roese .dram_sdqs3 = 0x00000030, 49*5d6050fdSStefan Roese .dram_sdqs4 = 0x00000030, 50*5d6050fdSStefan Roese .dram_sdqs5 = 0x00000030, 51*5d6050fdSStefan Roese .dram_sdqs6 = 0x00000030, 52*5d6050fdSStefan Roese .dram_sdqs7 = 0x00000030, 53*5d6050fdSStefan Roese /* DQM[0:7]: Differential input, 40 ohm */ 54*5d6050fdSStefan Roese .dram_dqm0 = 0x00020030, 55*5d6050fdSStefan Roese .dram_dqm1 = 0x00020030, 56*5d6050fdSStefan Roese .dram_dqm2 = 0x00020030, 57*5d6050fdSStefan Roese .dram_dqm3 = 0x00020030, 58*5d6050fdSStefan Roese .dram_dqm4 = 0x00020030, 59*5d6050fdSStefan Roese .dram_dqm5 = 0x00020030, 60*5d6050fdSStefan Roese .dram_dqm6 = 0x00020030, 61*5d6050fdSStefan Roese .dram_dqm7 = 0x00020030, 62*5d6050fdSStefan Roese }; 63*5d6050fdSStefan Roese 64*5d6050fdSStefan Roese /* Configure MX6Q/DUAL mmdc GRP io registers */ 65*5d6050fdSStefan Roese struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { 66*5d6050fdSStefan Roese /* DDR3 */ 67*5d6050fdSStefan Roese .grp_ddr_type = 0x000c0000, 68*5d6050fdSStefan Roese .grp_ddrmode_ctl = 0x00020000, 69*5d6050fdSStefan Roese /* disable DDR pullups */ 70*5d6050fdSStefan Roese .grp_ddrpke = 0x00000000, 71*5d6050fdSStefan Roese /* ADDR[00:16], SDBA[0:1]: 40 ohm */ 72*5d6050fdSStefan Roese .grp_addds = 0x00000030, 73*5d6050fdSStefan Roese /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ 74*5d6050fdSStefan Roese .grp_ctlds = 0x00000030, 75*5d6050fdSStefan Roese /* DATA[00:63]: Differential input, 40 ohm */ 76*5d6050fdSStefan Roese .grp_ddrmode = 0x00020000, 77*5d6050fdSStefan Roese .grp_b0ds = 0x00000030, 78*5d6050fdSStefan Roese .grp_b1ds = 0x00000030, 79*5d6050fdSStefan Roese .grp_b2ds = 0x00000030, 80*5d6050fdSStefan Roese .grp_b3ds = 0x00000030, 81*5d6050fdSStefan Roese .grp_b4ds = 0x00000030, 82*5d6050fdSStefan Roese .grp_b5ds = 0x00000030, 83*5d6050fdSStefan Roese .grp_b6ds = 0x00000030, 84*5d6050fdSStefan Roese .grp_b7ds = 0x00000030, 85*5d6050fdSStefan Roese }; 86*5d6050fdSStefan Roese 87*5d6050fdSStefan Roese /* MT41K256M16HA-125 */ 88*5d6050fdSStefan Roese static struct mx6_ddr3_cfg mt41k256m16ha_125 = { 89*5d6050fdSStefan Roese .mem_speed = 1600, 90*5d6050fdSStefan Roese .density = 4, /* 4Gbit */ 91*5d6050fdSStefan Roese .width = 16, 92*5d6050fdSStefan Roese .banks = 8, 93*5d6050fdSStefan Roese .rowaddr = 15, 94*5d6050fdSStefan Roese .coladdr = 10, 95*5d6050fdSStefan Roese .pagesz = 2, 96*5d6050fdSStefan Roese .trcd = 1375, 97*5d6050fdSStefan Roese .trcmin = 4875, 98*5d6050fdSStefan Roese .trasmin = 3500, 99*5d6050fdSStefan Roese }; 100*5d6050fdSStefan Roese 101*5d6050fdSStefan Roese /* 102*5d6050fdSStefan Roese * Values from running the Freescale DDR stress tool via USB 103*5d6050fdSStefan Roese */ 104*5d6050fdSStefan Roese static struct mx6_mmdc_calibration mx6dq_mmdc_calib = { 105*5d6050fdSStefan Roese /* write leveling calibration determine */ 106*5d6050fdSStefan Roese .p0_mpwldectrl0 = 0x0044004E, 107*5d6050fdSStefan Roese .p0_mpwldectrl1 = 0x001F0023, 108*5d6050fdSStefan Roese /* Read DQS Gating calibration */ 109*5d6050fdSStefan Roese .p0_mpdgctrl0 = 0x02480248, 110*5d6050fdSStefan Roese .p0_mpdgctrl1 = 0x0210021C, 111*5d6050fdSStefan Roese /* Read Calibration: DQS delay relative to DQ read access */ 112*5d6050fdSStefan Roese .p0_mprddlctl = 0x42444444, 113*5d6050fdSStefan Roese /* Write Calibration: DQ/DM delay relative to DQS write access */ 114*5d6050fdSStefan Roese .p0_mpwrdlctl = 0x36322C32, 115*5d6050fdSStefan Roese }; 116*5d6050fdSStefan Roese 117*5d6050fdSStefan Roese static void spl_dram_init(int width) 118*5d6050fdSStefan Roese { 119*5d6050fdSStefan Roese struct mx6_ddr3_cfg *mem = &mt41k256m16ha_125; 120*5d6050fdSStefan Roese struct mx6_ddr_sysinfo sysinfo = { 121*5d6050fdSStefan Roese /* width of data bus:0=16,1=32,2=64 */ 122*5d6050fdSStefan Roese .dsize = width / 32, 123*5d6050fdSStefan Roese /* config for full 4GB range so that get_mem_size() works */ 124*5d6050fdSStefan Roese .cs_density = 32, /* 32Gb per CS */ 125*5d6050fdSStefan Roese /* single chip select */ 126*5d6050fdSStefan Roese .ncs = 1, 127*5d6050fdSStefan Roese .cs1_mirror = 1, 128*5d6050fdSStefan Roese .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ 129*5d6050fdSStefan Roese #ifdef RTT_NOM_120OHM 130*5d6050fdSStefan Roese .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ 131*5d6050fdSStefan Roese #else 132*5d6050fdSStefan Roese .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ 133*5d6050fdSStefan Roese #endif 134*5d6050fdSStefan Roese .walat = 0, /* Write additional latency */ 135*5d6050fdSStefan Roese .ralat = 5, /* Read additional latency */ 136*5d6050fdSStefan Roese .mif3_mode = 3, /* Command prediction working mode */ 137*5d6050fdSStefan Roese .bi_on = 1, /* Bank interleaving enabled */ 138*5d6050fdSStefan Roese .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 139*5d6050fdSStefan Roese .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 140*5d6050fdSStefan Roese }; 141*5d6050fdSStefan Roese 142*5d6050fdSStefan Roese mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); 143*5d6050fdSStefan Roese mx6_dram_cfg(&sysinfo, &mx6dq_mmdc_calib, mem); 144*5d6050fdSStefan Roese } 145*5d6050fdSStefan Roese 146*5d6050fdSStefan Roese /* 147*5d6050fdSStefan Roese * Called from C runtime startup code (arch/arm/lib/crt0.S:_main) 148*5d6050fdSStefan Roese * - we have a stack and a place to store GD, both in SRAM 149*5d6050fdSStefan Roese * - no variable global data is available 150*5d6050fdSStefan Roese */ 151*5d6050fdSStefan Roese void board_init_f(ulong dummy) 152*5d6050fdSStefan Roese { 153*5d6050fdSStefan Roese /* Setup AIPS and disable watchdog */ 154*5d6050fdSStefan Roese arch_cpu_init(); 155*5d6050fdSStefan Roese 156*5d6050fdSStefan Roese ccgr_init(); 157*5d6050fdSStefan Roese gpr_init(); 158*5d6050fdSStefan Roese 159*5d6050fdSStefan Roese /* UART iomux */ 160*5d6050fdSStefan Roese board_early_init_f(); 161*5d6050fdSStefan Roese 162*5d6050fdSStefan Roese /* Setup GP timer */ 163*5d6050fdSStefan Roese timer_init(); 164*5d6050fdSStefan Roese 165*5d6050fdSStefan Roese /* UART clocks enabled and gd valid - init serial console */ 166*5d6050fdSStefan Roese preloader_console_init(); 167*5d6050fdSStefan Roese 168*5d6050fdSStefan Roese /* Init DDR with 32bit width */ 169*5d6050fdSStefan Roese spl_dram_init(32); 170*5d6050fdSStefan Roese 171*5d6050fdSStefan Roese /* Clear the BSS */ 172*5d6050fdSStefan Roese memset(__bss_start, 0, __bss_end - __bss_start); 173*5d6050fdSStefan Roese 174*5d6050fdSStefan Roese /* 175*5d6050fdSStefan Roese * Setup enet related MUXing early to give the PHY 176*5d6050fdSStefan Roese * some time to wake-up from reset 177*5d6050fdSStefan Roese */ 178*5d6050fdSStefan Roese platinum_setup_enet(); 179*5d6050fdSStefan Roese 180*5d6050fdSStefan Roese /* load/boot image from boot device */ 181*5d6050fdSStefan Roese board_init_r(NULL, 0); 182*5d6050fdSStefan Roese } 183