1 /*
2  * Copyright (C) 2014, Barco (www.barco.com)
3  * Copyright (C) 2014 Stefan Roese <sr@denx.de>
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #include <common.h>
9 #include <asm/arch/iomux.h>
10 #include <asm/arch/mx6-pins.h>
11 #include <asm/gpio.h>
12 #include <asm/mach-imx/iomux-v3.h>
13 #include <asm/mach-imx/mxc_i2c.h>
14 #include <miiphy.h>
15 #include <micrel.h>
16 
17 #include "platinum.h"
18 
19 iomux_v3_cfg_t const ecspi1_pads[] = {
20 	MX6_PAD_EIM_D16__ECSPI1_SCLK		| MUX_PAD_CTRL(ECSPI1_PAD_CLK),
21 	MX6_PAD_EIM_D17__ECSPI1_MISO		| MUX_PAD_CTRL(ECSPI_PAD_MISO),
22 	MX6_PAD_EIM_D18__ECSPI1_MOSI		| MUX_PAD_CTRL(ECSPI_PAD_MOSI),
23 	MX6_PAD_CSI0_DAT7__ECSPI1_SS0		| MUX_PAD_CTRL(ECSPI_PAD_SS),
24 	/* non mounted spi nor flash for booting */
25 	MX6_PAD_EIM_D19__ECSPI1_SS1		| MUX_PAD_CTRL(NO_PAD_CTRL),
26 	MX6_PAD_EIM_D24__ECSPI1_SS2		| MUX_PAD_CTRL(ECSPI_PAD_SS),
27 	MX6_PAD_EIM_D25__ECSPI1_SS3		| MUX_PAD_CTRL(ECSPI_PAD_SS),
28 };
29 
30 iomux_v3_cfg_t const ecspi2_pads[] = {
31 	MX6_PAD_EIM_CS0__ECSPI2_SCLK		| MUX_PAD_CTRL(ECSPI2_PAD_CLK),
32 	MX6_PAD_EIM_OE__ECSPI2_MISO		| MUX_PAD_CTRL(ECSPI_PAD_MISO),
33 	MX6_PAD_EIM_CS1__ECSPI2_MOSI		| MUX_PAD_CTRL(ECSPI_PAD_MOSI),
34 	MX6_PAD_EIM_RW__ECSPI2_SS0		| MUX_PAD_CTRL(ECSPI_PAD_SS),
35 };
36 
37 iomux_v3_cfg_t const enet_pads1[] = {
38 	MX6_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
39 	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
40 	MX6_PAD_RGMII_TXC__RGMII_TXC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
41 	MX6_PAD_RGMII_TD0__RGMII_TD0		| MUX_PAD_CTRL(ENET_PAD_CTRL),
42 	MX6_PAD_RGMII_TD1__RGMII_TD1		| MUX_PAD_CTRL(ENET_PAD_CTRL),
43 	MX6_PAD_RGMII_TD2__RGMII_TD2		| MUX_PAD_CTRL(ENET_PAD_CTRL),
44 	MX6_PAD_RGMII_TD3__RGMII_TD3		| MUX_PAD_CTRL(ENET_PAD_CTRL),
45 	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
46 	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
47 	/* pin 35 - 1 (PHY_AD2) on reset */
48 	MX6_PAD_RGMII_RXC__GPIO6_IO30		| MUX_PAD_CTRL(NO_PAD_CTRL),
49 	/* pin 32 - 1 - (MODE0) all */
50 	MX6_PAD_RGMII_RD0__GPIO6_IO25		| MUX_PAD_CTRL(NO_PAD_CTRL),
51 	/* pin 31 - 1 - (MODE1) all */
52 	MX6_PAD_RGMII_RD1__GPIO6_IO27		| MUX_PAD_CTRL(NO_PAD_CTRL),
53 	/* pin 28 - 1 - (MODE2) all */
54 	MX6_PAD_RGMII_RD2__GPIO6_IO28		| MUX_PAD_CTRL(NO_PAD_CTRL),
55 	/* pin 27 - 1 - (MODE3) all */
56 	MX6_PAD_RGMII_RD3__GPIO6_IO29		| MUX_PAD_CTRL(NO_PAD_CTRL),
57 	/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
58 	MX6_PAD_RGMII_RX_CTL__GPIO6_IO24	| MUX_PAD_CTRL(NO_PAD_CTRL),
59 	/* pin 42 PHY nRST */
60 	MX6_PAD_EIM_D23__GPIO3_IO23		| MUX_PAD_CTRL(NO_PAD_CTRL),
61 };
62 
63 iomux_v3_cfg_t const enet_pads2[] = {
64 	MX6_PAD_RGMII_RXC__RGMII_RXC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
65 	MX6_PAD_RGMII_RD0__RGMII_RD0		| MUX_PAD_CTRL(ENET_PAD_CTRL),
66 	MX6_PAD_RGMII_RD1__RGMII_RD1		| MUX_PAD_CTRL(ENET_PAD_CTRL),
67 	MX6_PAD_RGMII_RD2__RGMII_RD2		| MUX_PAD_CTRL(ENET_PAD_CTRL),
68 	MX6_PAD_RGMII_RD3__RGMII_RD3		| MUX_PAD_CTRL(ENET_PAD_CTRL),
69 	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
70 };
71 
72 iomux_v3_cfg_t const uart1_pads[] = {
73 	MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
74 	MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
75 };
76 
77 iomux_v3_cfg_t const uart2_pads[] = {
78 	MX6_PAD_EIM_D26__UART2_TX_DATA   | MUX_PAD_CTRL(UART_PAD_CTRL),
79 	MX6_PAD_EIM_D27__UART2_RX_DATA   | MUX_PAD_CTRL(UART_PAD_CTRL),
80 	MX6_PAD_EIM_D28__UART2_DTE_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
81 	MX6_PAD_EIM_D29__UART2_RTS_B     | MUX_PAD_CTRL(UART_PAD_CTRL),
82 };
83 
84 iomux_v3_cfg_t const uart4_pads[] = {
85 	MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
86 	MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
87 	MX6_PAD_CSI0_DAT16__UART4_RTS_B   | MUX_PAD_CTRL(UART_PAD_CTRL),
88 	MX6_PAD_CSI0_DAT17__UART4_CTS_B   | MUX_PAD_CTRL(UART_PAD_CTRL),
89 };
90 
91 struct i2c_pads_info i2c_pad_info0 = {
92 	.scl = {
93 		.i2c_mode  = MX6_PAD_CSI0_DAT9__I2C1_SCL	| PC_SCL,
94 		.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27	| PC_SCL,
95 		.gp = IMX_GPIO_NR(5, 27)
96 	},
97 	.sda = {
98 		.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA		| PC,
99 		.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26	| PC,
100 		.gp = IMX_GPIO_NR(5, 26)
101 	 }
102 };
103 
104 struct i2c_pads_info i2c_pad_info2 = {
105 	.scl = {
106 		.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL		| PC_SCL,
107 		.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03		| PC_SCL,
108 		.gp = IMX_GPIO_NR(1, 3)
109 	},
110 	.sda = {
111 		.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA		| PC,
112 		.gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11	| PC,
113 		.gp = IMX_GPIO_NR(7, 11)
114 	 }
115 };
116 
117 /*
118  * This enet related pin-muxing and GPIO handling is done
119  * in SPL U-Boot. For early initialization. And to give the
120  * PHY some time to come out of reset before the U-Boot
121  * ethernet driver tries to access its registers via MDIO.
122  */
123 int platinum_setup_enet(void)
124 {
125 	gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
126 	gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
127 	gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
128 	gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
129 	gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
130 	gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
131 	imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
132 	gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
133 
134 	/* Need delay 10ms according to KSZ9021 spec */
135 	mdelay(10);
136 	gpio_set_value(IMX_GPIO_NR(3, 23), 1);
137 	udelay(100);
138 
139 	imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
140 
141 	return 0;
142 }
143 
144 int platinum_setup_i2c(void)
145 {
146 	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
147 	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
148 
149 	return 0;
150 }
151 
152 int platinum_setup_spi(void)
153 {
154 	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
155 	imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads));
156 
157 	return 0;
158 }
159 
160 int platinum_setup_uart(void)
161 {
162 	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
163 	imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
164 	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
165 
166 	return 0;
167 }
168 
169 int platinum_phy_config(struct phy_device *phydev)
170 {
171 	/* min rx data delay */
172 	ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
173 				   0x0);
174 	/* min tx data delay */
175 	ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
176 				   0x0);
177 	/* max rx/tx clock delay, min rx/tx control */
178 	ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
179 				   0xf0f0);
180 	if (phydev->drv->config)
181 		phydev->drv->config(phydev);
182 
183 	return 0;
184 }
185 
186 int platinum_init_gpio(void)
187 {
188 	/* Default GPIO's */
189 	/* Toggle CONFIG_n to reset fpga on every boot */
190 	gpio_direction_output(IMX_GPIO_NR(5, 18), 0);
191 	/* Need delay >=2uS */
192 	udelay(3);
193 	gpio_set_value(IMX_GPIO_NR(5, 18), 1);
194 
195 	/* Default pin 1,15 high - DLP_FLASH_WPZ */
196 	gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
197 
198 	return 0;
199 }
200 
201 int platinum_init_usb(void)
202 {
203 	return 0;
204 }
205 
206 int platinum_init_finished(void)
207 {
208 	return 0;
209 }
210