1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2014, Barco (www.barco.com) 4 * Copyright (C) 2014 Stefan Roese <sr@denx.de> 5 */ 6 7 #include <common.h> 8 #include <mmc.h> 9 #include <fsl_esdhc.h> 10 #include <miiphy.h> 11 #include <netdev.h> 12 #include <asm/io.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch/imx-regs.h> 15 #include <asm/arch/iomux.h> 16 #include <asm/arch/mx6-pins.h> 17 #include <asm/arch/crm_regs.h> 18 #include <asm/arch/sys_proto.h> 19 #include <asm/gpio.h> 20 #include <asm/mach-imx/iomux-v3.h> 21 #include <asm/mach-imx/boot_mode.h> 22 23 #include "platinum.h" 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 iomux_v3_cfg_t const usdhc3_pads[] = { 28 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 29 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 30 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 31 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 32 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 33 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 34 MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 35 }; 36 37 iomux_v3_cfg_t nfc_pads[] = { 38 MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), 39 MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), 40 MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL), 41 MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL), 42 MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL), 43 MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL), 44 MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL), 45 MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL), 46 MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL), 47 MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL), 48 MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL), 49 MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL), 50 MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL), 51 MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL), 52 MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL), 53 MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL), 54 MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL), 55 MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL), 56 MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL), 57 }; 58 59 struct fsl_esdhc_cfg usdhc_cfg[] = { 60 { USDHC3_BASE_ADDR }, 61 }; 62 63 void setup_gpmi_nand(void) 64 { 65 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 66 67 /* config gpmi nand iomux */ 68 imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads)); 69 70 /* config gpmi and bch clock to 100 MHz */ 71 clrsetbits_le32(&mxc_ccm->cs2cdr, 72 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | 73 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | 74 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, 75 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | 76 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | 77 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); 78 79 /* enable gpmi and bch clock gating */ 80 setbits_le32(&mxc_ccm->CCGR4, 81 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | 82 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | 83 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | 84 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | 85 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); 86 87 /* enable apbh clock gating */ 88 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); 89 } 90 91 int dram_init(void) 92 { 93 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); 94 95 return 0; 96 } 97 98 int board_ehci_hcd_init(int port) 99 { 100 return 0; 101 } 102 103 int board_mmc_getcd(struct mmc *mmc) 104 { 105 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 106 107 if (cfg->esdhc_base == usdhc_cfg[0].esdhc_base) { 108 unsigned sd3_cd = IMX_GPIO_NR(7, 0); 109 gpio_direction_input(sd3_cd); 110 return !gpio_get_value(sd3_cd); 111 } 112 113 return 0; 114 } 115 116 int board_mmc_init(bd_t *bis) 117 { 118 imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 119 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 120 121 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); 122 } 123 124 void board_init_gpio(void) 125 { 126 platinum_init_gpio(); 127 } 128 129 void board_init_gpmi_nand(void) 130 { 131 setup_gpmi_nand(); 132 } 133 134 void board_init_i2c(void) 135 { 136 platinum_setup_i2c(); 137 } 138 139 void board_init_spi(void) 140 { 141 platinum_setup_spi(); 142 } 143 144 void board_init_uart(void) 145 { 146 platinum_setup_uart(); 147 } 148 149 void board_init_usb(void) 150 { 151 platinum_init_usb(); 152 } 153 154 void board_init_finished(void) 155 { 156 platinum_init_finished(); 157 } 158 159 int board_phy_config(struct phy_device *phydev) 160 { 161 return platinum_phy_config(phydev); 162 } 163 164 int board_eth_init(bd_t *bis) 165 { 166 return cpu_eth_init(bis); 167 } 168 169 int board_early_init_f(void) 170 { 171 board_init_uart(); 172 173 return 0; 174 } 175 176 int board_init(void) 177 { 178 /* address of boot parameters */ 179 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 180 181 board_init_spi(); 182 183 board_init_i2c(); 184 185 board_init_gpmi_nand(); 186 187 board_init_gpio(); 188 189 board_init_usb(); 190 191 board_init_finished(); 192 193 return 0; 194 } 195 196 int checkboard(void) 197 { 198 puts("Board: " CONFIG_PLATINUM_BOARD "\n"); 199 return 0; 200 } 201 202 static const struct boot_mode board_boot_modes[] = { 203 /* NAND */ 204 { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) }, 205 /* 4 bit bus width */ 206 { "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) }, 207 { "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) }, 208 { NULL, 0 }, 209 }; 210 211 int misc_init_r(void) 212 { 213 add_board_boot_modes(board_boot_modes); 214 215 return 0; 216 } 217