1 /*
2  * Copyright (C) 2015, Bachmann electronic GmbH
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <spl.h>
9 #include <asm/arch/mx6-ddr.h>
10 
11 DECLARE_GLOBAL_DATA_PTR;
12 
13 /* Configure MX6Q/DUAL mmdc DDR io registers */
14 static struct mx6dq_iomux_ddr_regs ot1200_ddr_ioregs = {
15 	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 48ohm */
16 	.dram_sdclk_0   = 0x00000028,
17 	.dram_sdclk_1   = 0x00000028,
18 	.dram_cas       = 0x00000028,
19 	.dram_ras       = 0x00000028,
20 	.dram_reset     = 0x00000028,
21 	/* SDCKE[0:1]: 100k pull-up */
22 	.dram_sdcke0    = 0x00003000,
23 	.dram_sdcke1    = 0x00003000,
24 	/* SDBA2: pull-up disabled */
25 	.dram_sdba2	    = 0x00000000,
26 	/* SDODT[0:1]: 100k pull-up, 48 ohm */
27 	.dram_sdodt0    = 0x00000028,
28 	.dram_sdodt1    = 0x00000028,
29 	/* SDQS[0:7]: Differential input, 48 ohm */
30 	.dram_sdqs0     = 0x00000028,
31 	.dram_sdqs1     = 0x00000028,
32 	.dram_sdqs2     = 0x00000028,
33 	.dram_sdqs3     = 0x00000028,
34 	.dram_sdqs4     = 0x00000028,
35 	.dram_sdqs5     = 0x00000028,
36 	.dram_sdqs6     = 0x00000028,
37 	.dram_sdqs7     = 0x00000028,
38 	/* DQM[0:7]: Differential input, 48 ohm */
39 	.dram_dqm0      = 0x00000028,
40 	.dram_dqm1      = 0x00000028,
41 	.dram_dqm2      = 0x00000028,
42 	.dram_dqm3      = 0x00000028,
43 	.dram_dqm4      = 0x00000028,
44 	.dram_dqm5      = 0x00000028,
45 	.dram_dqm6      = 0x00000028,
46 	.dram_dqm7      = 0x00000028,
47 };
48 
49 /* Configure MX6Q/DUAL mmdc GRP io registers */
50 static struct mx6dq_iomux_grp_regs ot1200_grp_ioregs = {
51 	/* DDR3 */
52 	.grp_ddr_type    = 0x000c0000,
53 	.grp_ddrmode_ctl = 0x00020000,
54 	/* Disable DDR pullups */
55 	.grp_ddrpke      = 0x00000000,
56 	/* ADDR[00:16], SDBA[0:1]: 48 ohm */
57 	.grp_addds       = 0x00000028,
58 	/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 48 ohm */
59 	.grp_ctlds       = 0x00000028,
60 	/* DATA[00:63]: Differential input, 48 ohm */
61 	.grp_ddrmode     = 0x00020000,
62 	.grp_b0ds        = 0x00000028,
63 	.grp_b1ds        = 0x00000028,
64 	.grp_b2ds        = 0x00000028,
65 	.grp_b3ds        = 0x00000028,
66 	.grp_b4ds        = 0x00000028,
67 	.grp_b5ds        = 0x00000028,
68 	.grp_b6ds        = 0x00000028,
69 	.grp_b7ds        = 0x00000028,
70 };
71 
72 static struct mx6_ddr_sysinfo ot1200_ddr_sysinfo = {
73 	/* Width of data bus: 0=16, 1=32, 2=64 */
74 	.dsize      = 2,
75 	/* config for full 4GB range so that get_mem_size() works */
76 	.cs_density = 32, /* 32Gb per CS */
77 	/* Single chip select */
78 	.ncs        = 1,
79 	.cs1_mirror = 0,	/* war 0 */
80 	.rtt_wr     = 1,	/* DDR3_RTT_60_OHM - RTT_Wr = RZQ/4 */
81 	.rtt_nom    = 1,	/* DDR3_RTT_60_OHM - RTT_Nom = RZQ/4 */
82 	.walat      = 1,	/* Write additional latency */
83 	.ralat      = 5,	/* Read additional latency */
84 	.mif3_mode  = 3,	/* Command prediction working mode */
85 	.bi_on      = 1,	/* Bank interleaving enabled */	/* war 1 */
86 	.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
87 	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
88 	.refsel = 1,		/* Refresh cycles at 32KHz */
89 	.refr = 7,		/* 8 refresh commands per refresh cycle */
90 };
91 
92 /* MT41K128M16JT-125 */
93 static struct mx6_ddr3_cfg micron_2gib_1600 = {
94 	.mem_speed = 1600,
95 	.density   = 2,
96 	.width     = 16,
97 	.banks     = 8,
98 	.rowaddr   = 14,
99 	.coladdr   = 10,
100 	.pagesz    = 2,
101 	.trcd      = 1375,
102 	.trcmin    = 4875,
103 	.trasmin   = 3500,
104 	.SRT       = 1,
105 };
106 
107 static struct mx6_mmdc_calibration micron_2gib_1600_mmdc_calib = {
108 	/* write leveling calibration determine */
109 	.p0_mpwldectrl0 = 0x00260025,
110 	.p0_mpwldectrl1 = 0x00270021,
111 	.p1_mpwldectrl0 = 0x00180034,
112 	.p1_mpwldectrl1 = 0x00180024,
113 	/* Read DQS Gating calibration */
114 	.p0_mpdgctrl0   = 0x04380344,
115 	.p0_mpdgctrl1   = 0x0330032C,
116 	.p1_mpdgctrl0   = 0x0338033C,
117 	.p1_mpdgctrl1   = 0x032C0300,
118 	/* Read Calibration: DQS delay relative to DQ read access */
119 	.p0_mprddlctl   = 0x3C2E3238,
120 	.p1_mprddlctl   = 0x3A2E303C,
121 	/* Write Calibration: DQ/DM delay relative to DQS write access */
122 	.p0_mpwrdlctl   = 0x36384036,
123 	.p1_mpwrdlctl   = 0x442E4438,
124 };
125 
126 static void ot1200_spl_dram_init(void)
127 {
128 	mx6dq_dram_iocfg(64, &ot1200_ddr_ioregs, &ot1200_grp_ioregs);
129 	mx6_dram_cfg(&ot1200_ddr_sysinfo, &micron_2gib_1600_mmdc_calib,
130 		     &micron_2gib_1600);
131 }
132 
133 /*
134  * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
135  * - we have a stack and a place to store GD, both in SRAM
136  * - no variable global data is available
137  */
138 void board_init_f(ulong dummy)
139 {
140 	/* setup AIPS and disable watchdog */
141 	arch_cpu_init();
142 
143 	/* iomux and setup of i2c */
144 	board_early_init_f();
145 
146 	/* setup GP timer */
147 	timer_init();
148 
149 	/* UART clocks enabled and gd valid - init serial console */
150 	preloader_console_init();
151 
152 	/* configure MMDC for SDRAM width/size and per-model calibration */
153 	ot1200_spl_dram_init();
154 
155 	/* Clear the BSS. */
156 	memset(__bss_start, 0, __bss_end - __bss_start);
157 
158 	/* load/boot image from boot device */
159 	board_init_r(NULL, 0);
160 }
161