1 /* 2 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. 3 * Copyright (C) 2014, Bachmann electronic GmbH 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <asm/arch/clock.h> 11 #include <asm/arch/imx-regs.h> 12 #include <asm/arch/iomux.h> 13 #include <malloc.h> 14 #include <asm/arch/mx6-pins.h> 15 #include <asm/imx-common/iomux-v3.h> 16 #include <asm/imx-common/sata.h> 17 #include <asm/imx-common/mxc_i2c.h> 18 #include <asm/imx-common/boot_mode.h> 19 #include <asm/arch/crm_regs.h> 20 #include <asm/arch/sys_proto.h> 21 #include <mmc.h> 22 #include <fsl_esdhc.h> 23 #include <netdev.h> 24 #include <i2c.h> 25 #include <pca953x.h> 26 #include <asm/gpio.h> 27 #include <phy.h> 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) 32 33 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 34 OUTPUT_40OHM | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 35 36 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ 37 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ 38 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 39 40 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \ 41 PAD_CTL_HYS) 42 43 #define SPI_PAD_CTRL (PAD_CTL_HYS | OUTPUT_40OHM | \ 44 PAD_CTL_SRE_FAST) 45 46 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \ 47 PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST) 48 49 int dram_init(void) 50 { 51 gd->ram_size = imx_ddr_size(); 52 53 return 0; 54 } 55 56 static iomux_v3_cfg_t const uart1_pads[] = { 57 MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 58 MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 59 }; 60 61 static void setup_iomux_uart(void) 62 { 63 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 64 } 65 66 static iomux_v3_cfg_t const enet_pads[] = { 67 MX6_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(ENET_PAD_CTRL), 68 MX6_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL), 69 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 70 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 71 MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 72 MX6_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 73 MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 74 MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 75 MX6_PAD_KEY_COL2__ENET_RX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 76 MX6_PAD_KEY_COL0__ENET_RX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 77 MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 78 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 79 MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 80 MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 81 MX6_PAD_KEY_ROW2__ENET_TX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 82 MX6_PAD_KEY_ROW0__ENET_TX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 83 MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 84 }; 85 86 static void setup_iomux_enet(void) 87 { 88 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); 89 } 90 91 static iomux_v3_cfg_t const ecspi1_pads[] = { 92 MX6_PAD_DISP0_DAT3__ECSPI3_SS0 | MUX_PAD_CTRL(SPI_PAD_CTRL), 93 MX6_PAD_DISP0_DAT4__ECSPI3_SS1 | MUX_PAD_CTRL(SPI_PAD_CTRL), 94 MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), 95 MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), 96 MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), 97 }; 98 99 static void setup_iomux_spi(void) 100 { 101 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); 102 } 103 104 int board_spi_cs_gpio(unsigned bus, unsigned cs) 105 { 106 return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(1, 3)) : -1; 107 } 108 109 static iomux_v3_cfg_t const feature_pads[] = { 110 /* SD card detect */ 111 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_DOWN), 112 113 /* eMMC soldered? */ 114 MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP), 115 }; 116 117 static void setup_iomux_features(void) 118 { 119 imx_iomux_v3_setup_multiple_pads(feature_pads, 120 ARRAY_SIZE(feature_pads)); 121 } 122 123 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 124 125 /* I2C2 - EEPROM */ 126 static struct i2c_pads_info i2c_pad_info1 = { 127 .scl = { 128 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC, 129 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC, 130 .gp = IMX_GPIO_NR(2, 30) 131 }, 132 .sda = { 133 .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC, 134 .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC, 135 .gp = IMX_GPIO_NR(3, 16) 136 } 137 }; 138 139 /* I2C3 - IO expander */ 140 static struct i2c_pads_info i2c_pad_info2 = { 141 .scl = { 142 .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC, 143 .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC, 144 .gp = IMX_GPIO_NR(3, 17) 145 }, 146 .sda = { 147 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, 148 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, 149 .gp = IMX_GPIO_NR(3, 18) 150 } 151 }; 152 153 static void setup_iomux_i2c(void) 154 { 155 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 156 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); 157 } 158 159 static void ccgr_init(void) 160 { 161 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 162 163 writel(0x00C03F3F, &ccm->CCGR0); 164 writel(0x0030FC33, &ccm->CCGR1); 165 writel(0x0FFFC000, &ccm->CCGR2); 166 writel(0x3FF00000, &ccm->CCGR3); 167 writel(0x00FFF300, &ccm->CCGR4); 168 writel(0x0F0000C3, &ccm->CCGR5); 169 writel(0x000003FF, &ccm->CCGR6); 170 } 171 172 static void gpr_init(void) 173 { 174 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 175 176 /* enable AXI cache for VDOA/VPU/IPU */ 177 writel(0xF00000CF, &iomux->gpr[4]); 178 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ 179 writel(0x007F007F, &iomux->gpr[6]); 180 writel(0x007F007F, &iomux->gpr[7]); 181 } 182 183 int board_early_init_f(void) 184 { 185 ccgr_init(); 186 gpr_init(); 187 188 setup_iomux_uart(); 189 setup_iomux_spi(); 190 setup_iomux_i2c(); 191 setup_iomux_features(); 192 193 return 0; 194 } 195 196 static iomux_v3_cfg_t const usdhc3_pads[] = { 197 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 198 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 199 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 200 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 201 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 202 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 203 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 204 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 205 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 206 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 207 MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL), 208 }; 209 210 iomux_v3_cfg_t const usdhc4_pads[] = { 211 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 212 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 213 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 214 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 215 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 216 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 217 }; 218 219 int board_mmc_getcd(struct mmc *mmc) 220 { 221 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 222 int ret; 223 224 if (cfg->esdhc_base == USDHC3_BASE_ADDR) { 225 gpio_direction_input(IMX_GPIO_NR(4, 5)); 226 ret = gpio_get_value(IMX_GPIO_NR(4, 5)); 227 } else { 228 gpio_direction_input(IMX_GPIO_NR(1, 5)); 229 ret = !gpio_get_value(IMX_GPIO_NR(1, 5)); 230 } 231 232 return ret; 233 } 234 235 struct fsl_esdhc_cfg usdhc_cfg[2] = { 236 {USDHC3_BASE_ADDR}, 237 {USDHC4_BASE_ADDR}, 238 }; 239 240 int board_mmc_init(bd_t *bis) 241 { 242 int ret; 243 u32 index = 0; 244 245 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 246 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 247 248 usdhc_cfg[0].max_bus_width = 8; 249 usdhc_cfg[1].max_bus_width = 4; 250 251 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { 252 switch (index) { 253 case 0: 254 imx_iomux_v3_setup_multiple_pads( 255 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 256 break; 257 case 1: 258 imx_iomux_v3_setup_multiple_pads( 259 usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); 260 break; 261 default: 262 printf("Warning: you configured more USDHC controllers" 263 "(%d) then supported by the board (%d)\n", 264 index + 1, CONFIG_SYS_FSL_USDHC_NUM); 265 return -EINVAL; 266 } 267 268 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); 269 if (ret) 270 return ret; 271 } 272 273 return 0; 274 } 275 276 static iomux_v3_cfg_t const pwm_pad[] = { 277 MX6_PAD_SD1_CMD__PWM4_OUT | MUX_PAD_CTRL(OUTPUT_40OHM), 278 }; 279 280 static void leds_on(void) 281 { 282 /* turn on all possible leds connected via GPIO expander */ 283 i2c_set_bus_num(2); 284 pca953x_set_dir(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, PCA953X_DIR_OUT); 285 pca953x_set_val(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, 0x0); 286 } 287 288 static void backlight_lcd_off(void) 289 { 290 unsigned gpio = IMX_GPIO_NR(2, 0); 291 gpio_direction_output(gpio, 0); 292 293 gpio = IMX_GPIO_NR(2, 3); 294 gpio_direction_output(gpio, 0); 295 } 296 297 int board_eth_init(bd_t *bis) 298 { 299 uint32_t base = IMX_FEC_BASE; 300 struct mii_dev *bus = NULL; 301 struct phy_device *phydev = NULL; 302 int ret; 303 304 setup_iomux_enet(); 305 306 bus = fec_get_miibus(base, -1); 307 if (!bus) 308 return 0; 309 310 /* scan phy 0 and 5 */ 311 phydev = phy_find_by_mask(bus, 0x21, PHY_INTERFACE_MODE_RGMII); 312 if (!phydev) { 313 free(bus); 314 return 0; 315 } 316 317 /* depending on the phy address we can detect our board version */ 318 if (phydev->addr == 0) 319 setenv("boardver", ""); 320 else 321 setenv("boardver", "mr"); 322 323 printf("using phy at %d\n", phydev->addr); 324 ret = fec_probe(bis, -1, base, bus, phydev); 325 if (ret) { 326 printf("FEC MXC: %s:failed\n", __func__); 327 free(phydev); 328 free(bus); 329 } 330 return 0; 331 } 332 333 int board_init(void) 334 { 335 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 336 337 backlight_lcd_off(); 338 339 leds_on(); 340 341 #ifdef CONFIG_CMD_SATA 342 setup_sata(); 343 #endif 344 345 return 0; 346 } 347 348 int checkboard(void) 349 { 350 puts("Board: "CONFIG_SYS_BOARD"\n"); 351 return 0; 352 } 353 354 #ifdef CONFIG_CMD_BMODE 355 static const struct boot_mode board_boot_modes[] = { 356 /* 4 bit bus width */ 357 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, 358 {NULL, 0}, 359 }; 360 #endif 361 362 int misc_init_r(void) 363 { 364 #ifdef CONFIG_CMD_BMODE 365 add_board_boot_modes(board_boot_modes); 366 #endif 367 return 0; 368 } 369