1 /* 2 * (C) Copyright 2010,2011 3 * NVIDIA Corporation <www.nvidia.com> 4 * (C) Copyright 2011 5 * Avionic Design GmbH <www.avionic-design.de> 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <ns16550.h> 28 #include <asm/io.h> 29 #include <asm/gpio.h> 30 #include <asm/arch/tegra2.h> 31 #include <asm/arch/sys_proto.h> 32 #include <asm/arch/clk_rst.h> 33 #include <asm/arch/clock.h> 34 #include <asm/arch/pinmux.h> 35 #include <asm/arch/uart.h> 36 #include <asm/arch/mmc.h> 37 #include "tamonten.h" 38 39 #ifdef CONFIG_TEGRA2_MMC 40 #include <mmc.h> 41 #endif 42 43 DECLARE_GLOBAL_DATA_PTR; 44 45 const struct tegra2_sysinfo sysinfo = { 46 CONFIG_TEGRA2_BOARD_STRING 47 }; 48 49 /* 50 * Routine: timer_init 51 * Description: init the timestamp and lastinc value 52 */ 53 int timer_init(void) 54 { 55 return 0; 56 } 57 58 static void enable_uart(enum periph_id pid) 59 { 60 /* Assert UART reset and enable clock */ 61 reset_set_enable(pid, 1); 62 clock_enable(pid); 63 clock_ll_set_source(pid, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */ 64 65 /* wait for 2us */ 66 udelay(2); 67 68 /* De-assert reset to UART */ 69 reset_set_enable(pid, 0); 70 } 71 72 /* 73 * Routine: clock_init_uart 74 * Description: init the PLL and clock for the UART(s) 75 */ 76 static void clock_init_uart(void) 77 { 78 #if defined(CONFIG_TEGRA2_ENABLE_UARTD) 79 enable_uart(PERIPH_ID_UART4); 80 #endif /* CONFIG_TEGRA2_ENABLE_UARTD */ 81 } 82 83 /* 84 * Routine: pin_mux_uart 85 * Description: setup the pin muxes/tristate values for the UART(s) 86 */ 87 static void pin_mux_uart(void) 88 { 89 #if defined(CONFIG_TEGRA2_ENABLE_UARTD) 90 pinmux_set_func(PINGRP_GMC, PMUX_FUNC_UARTD); 91 92 pinmux_tristate_disable(PINGRP_GMC); 93 #endif /* CONFIG_TEGRA2_ENABLE_UARTD */ 94 } 95 96 #ifdef CONFIG_TEGRA2_MMC 97 /* 98 * Routine: pin_mux_mmc 99 * Description: setup the pin muxes/tristate values for the SDMMC(s) 100 */ 101 static void pin_mux_mmc(void) 102 { 103 /* SDMMC4: config 3, x8 on 2nd set of pins */ 104 pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4); 105 pinmux_set_func(PINGRP_GMA, PMUX_FUNC_SDIO4); 106 pinmux_set_func(PINGRP_GME, PMUX_FUNC_SDIO4); 107 108 pinmux_tristate_disable(PINGRP_ATB); 109 pinmux_tristate_disable(PINGRP_GMA); 110 pinmux_tristate_disable(PINGRP_GME); 111 } 112 #endif 113 114 /* 115 * Routine: board_init 116 * Description: Early hardware init. 117 */ 118 int board_init(void) 119 { 120 clock_init(); 121 clock_verify(); 122 123 /* boot param addr */ 124 gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100); 125 126 return 0; 127 } 128 129 #ifdef CONFIG_TEGRA2_MMC 130 /* this is a weak define that we are overriding */ 131 int board_mmc_init(bd_t *bd) 132 { 133 debug("board_mmc_init called\n"); 134 /* Enable muxes, etc. for SDMMC controllers */ 135 pin_mux_mmc(); 136 gpio_config_mmc(); 137 138 debug("board_mmc_init: init eMMC\n"); 139 /* init dev 0, eMMC chip, with 4-bit bus */ 140 tegra2_mmc_init(0, 4, -1, GPIO_PH2); 141 142 return 0; 143 } 144 #endif 145 146 #ifdef CONFIG_BOARD_EARLY_INIT_F 147 int board_early_init_f(void) 148 { 149 /* Initialize essential common plls */ 150 clock_early_init(); 151 152 /* Initialize UART clocks */ 153 clock_init_uart(); 154 155 /* Initialize periph pinmuxes */ 156 pin_mux_uart(); 157 158 return 0; 159 } 160 #endif /* EARLY_INIT */ 161