1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2014 Atmel 4 * Bo Shen <voice.shen@atmel.com> 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <asm/arch/at91_common.h> 10 #include <asm/arch/at91_rstc.h> 11 #include <asm/arch/atmel_mpddrc.h> 12 #include <asm/arch/gpio.h> 13 #include <asm/arch/clk.h> 14 #include <asm/arch/sama5d3_smc.h> 15 #include <asm/arch/sama5d4.h> 16 #include <debug_uart.h> 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 #ifdef CONFIG_NAND_ATMEL 21 static void sama5d4ek_nand_hw_init(void) 22 { 23 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 24 25 at91_periph_clk_enable(ATMEL_ID_SMC); 26 27 /* Configure SMC CS3 for NAND */ 28 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | 29 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1), 30 &smc->cs[3].setup); 31 writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) | 32 AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3), 33 &smc->cs[3].pulse); 34 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), 35 &smc->cs[3].cycle); 36 writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) | 37 AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) | 38 AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3)| 39 AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); 40 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 41 AT91_SMC_MODE_EXNW_DISABLE | 42 AT91_SMC_MODE_DBW_8 | 43 AT91_SMC_MODE_TDF_CYCLE(3), 44 &smc->cs[3].mode); 45 46 at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */ 47 at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */ 48 at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */ 49 at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */ 50 at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */ 51 at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */ 52 at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */ 53 at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */ 54 at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */ 55 at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */ 56 at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */ 57 at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */ 58 at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */ 59 at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */ 60 } 61 #endif 62 63 #ifdef CONFIG_CMD_USB 64 static void sama5d4ek_usb_hw_init(void) 65 { 66 at91_set_pio_output(AT91_PIO_PORTE, 11, 0); 67 at91_set_pio_output(AT91_PIO_PORTE, 12, 0); 68 at91_set_pio_output(AT91_PIO_PORTE, 10, 0); 69 } 70 #endif 71 72 #ifdef CONFIG_BOARD_LATE_INIT 73 int board_late_init(void) 74 { 75 #ifdef CONFIG_DM_VIDEO 76 at91_video_show_board_info(); 77 #endif 78 return 0; 79 } 80 #endif 81 82 #ifdef CONFIG_DEBUG_UART_BOARD_INIT 83 static void sama5d4ek_serial3_hw_init(void) 84 { 85 at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */ 86 at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */ 87 88 /* Enable clock */ 89 at91_periph_clk_enable(ATMEL_ID_USART3); 90 } 91 92 void board_debug_uart_init(void) 93 { 94 sama5d4ek_serial3_hw_init(); 95 } 96 #endif 97 98 #ifdef CONFIG_BOARD_EARLY_INIT_F 99 int board_early_init_f(void) 100 { 101 #ifdef CONFIG_DEBUG_UART 102 debug_uart_init(); 103 #endif 104 return 0; 105 } 106 #endif 107 108 int board_init(void) 109 { 110 /* adress of boot parameters */ 111 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 112 113 #ifdef CONFIG_NAND_ATMEL 114 sama5d4ek_nand_hw_init(); 115 #endif 116 #ifdef CONFIG_CMD_USB 117 sama5d4ek_usb_hw_init(); 118 #endif 119 120 return 0; 121 } 122 123 int dram_init(void) 124 { 125 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 126 CONFIG_SYS_SDRAM_SIZE); 127 return 0; 128 } 129 130 /* SPL */ 131 #ifdef CONFIG_SPL_BUILD 132 void spl_board_init(void) 133 { 134 #if CONFIG_NAND_BOOT 135 sama5d4ek_nand_hw_init(); 136 #endif 137 } 138 139 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) 140 { 141 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); 142 143 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | 144 ATMEL_MPDDRC_CR_NR_ROW_14 | 145 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | 146 ATMEL_MPDDRC_CR_NB_8BANKS | 147 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | 148 ATMEL_MPDDRC_CR_UNAL_SUPPORTED); 149 150 ddr2->rtr = 0x2b0; 151 152 ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | 153 3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | 154 3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | 155 10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | 156 3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | 157 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | 158 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | 159 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); 160 161 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | 162 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | 163 25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | 164 23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); 165 166 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | 167 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | 168 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | 169 2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | 170 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); 171 } 172 173 void mem_init(void) 174 { 175 struct atmel_mpddrc_config ddr2; 176 const struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; 177 u32 tmp; 178 179 ddr2_conf(&ddr2); 180 181 /* Enable MPDDR clock */ 182 at91_periph_clk_enable(ATMEL_ID_MPDDRC); 183 at91_system_clk_enable(AT91_PMC_DDR); 184 185 tmp = ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE; 186 writel(tmp, &mpddr->rd_data_path); 187 188 tmp = readl(&mpddr->io_calibr); 189 tmp = (tmp & ~(ATMEL_MPDDRC_IO_CALIBR_RDIV | 190 ATMEL_MPDDRC_IO_CALIBR_TZQIO | 191 ATMEL_MPDDRC_IO_CALIBR_CALCODEP | 192 ATMEL_MPDDRC_IO_CALIBR_CALCODEN)) | 193 ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_52 | 194 ATMEL_MPDDRC_IO_CALIBR_TZQIO_(8) | 195 ATMEL_MPDDRC_IO_CALIBR_EN_CALIB; 196 writel(tmp, &mpddr->io_calibr); 197 198 /* DDRAM2 Controller initialize */ 199 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); 200 } 201 202 void at91_pmc_init(void) 203 { 204 u32 tmp; 205 206 tmp = AT91_PMC_PLLAR_29 | 207 AT91_PMC_PLLXR_PLLCOUNT(0x3f) | 208 AT91_PMC_PLLXR_MUL(87) | 209 AT91_PMC_PLLXR_DIV(1); 210 at91_plla_init(tmp); 211 212 at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x0)); 213 214 tmp = AT91_PMC_MCKR_H32MXDIV | 215 AT91_PMC_MCKR_PLLADIV_2 | 216 AT91_PMC_MCKR_MDIV_3 | 217 AT91_PMC_MCKR_CSS_PLLA; 218 at91_mck_init(tmp); 219 } 220 #endif 221