1 /* 2 * Copyright (C) 2014 Atmel 3 * Bo Shen <voice.shen@atmel.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <asm/arch/at91_common.h> 11 #include <asm/arch/at91_rstc.h> 12 #include <asm/arch/atmel_mpddrc.h> 13 #include <asm/arch/gpio.h> 14 #include <asm/arch/clk.h> 15 #include <asm/arch/sama5d3_smc.h> 16 #include <asm/arch/sama5d4.h> 17 #include <debug_uart.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 #ifdef CONFIG_NAND_ATMEL 22 static void sama5d4ek_nand_hw_init(void) 23 { 24 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 25 26 at91_periph_clk_enable(ATMEL_ID_SMC); 27 28 /* Configure SMC CS3 for NAND */ 29 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | 30 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1), 31 &smc->cs[3].setup); 32 writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) | 33 AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3), 34 &smc->cs[3].pulse); 35 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), 36 &smc->cs[3].cycle); 37 writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) | 38 AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) | 39 AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3)| 40 AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); 41 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 42 AT91_SMC_MODE_EXNW_DISABLE | 43 AT91_SMC_MODE_DBW_8 | 44 AT91_SMC_MODE_TDF_CYCLE(3), 45 &smc->cs[3].mode); 46 47 at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */ 48 at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */ 49 at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */ 50 at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */ 51 at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */ 52 at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */ 53 at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */ 54 at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */ 55 at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */ 56 at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */ 57 at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */ 58 at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */ 59 at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */ 60 at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */ 61 } 62 #endif 63 64 #ifdef CONFIG_CMD_USB 65 static void sama5d4ek_usb_hw_init(void) 66 { 67 at91_set_pio_output(AT91_PIO_PORTE, 11, 0); 68 at91_set_pio_output(AT91_PIO_PORTE, 12, 0); 69 at91_set_pio_output(AT91_PIO_PORTE, 10, 0); 70 } 71 #endif 72 73 #ifdef CONFIG_BOARD_LATE_INIT 74 int board_late_init(void) 75 { 76 #ifdef CONFIG_DM_VIDEO 77 at91_video_show_board_info(); 78 #endif 79 return 0; 80 } 81 #endif 82 83 #ifdef CONFIG_DEBUG_UART_BOARD_INIT 84 static void sama5d4ek_serial3_hw_init(void) 85 { 86 at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */ 87 at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */ 88 89 /* Enable clock */ 90 at91_periph_clk_enable(ATMEL_ID_USART3); 91 } 92 93 void board_debug_uart_init(void) 94 { 95 sama5d4ek_serial3_hw_init(); 96 } 97 #endif 98 99 #ifdef CONFIG_BOARD_EARLY_INIT_F 100 int board_early_init_f(void) 101 { 102 #ifdef CONFIG_DEBUG_UART 103 debug_uart_init(); 104 #endif 105 return 0; 106 } 107 #endif 108 109 int board_init(void) 110 { 111 /* adress of boot parameters */ 112 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 113 114 #ifdef CONFIG_NAND_ATMEL 115 sama5d4ek_nand_hw_init(); 116 #endif 117 #ifdef CONFIG_CMD_USB 118 sama5d4ek_usb_hw_init(); 119 #endif 120 121 return 0; 122 } 123 124 int dram_init(void) 125 { 126 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 127 CONFIG_SYS_SDRAM_SIZE); 128 return 0; 129 } 130 131 /* SPL */ 132 #ifdef CONFIG_SPL_BUILD 133 void spl_board_init(void) 134 { 135 #if CONFIG_NAND_BOOT 136 sama5d4ek_nand_hw_init(); 137 #endif 138 } 139 140 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) 141 { 142 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); 143 144 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | 145 ATMEL_MPDDRC_CR_NR_ROW_14 | 146 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | 147 ATMEL_MPDDRC_CR_NB_8BANKS | 148 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | 149 ATMEL_MPDDRC_CR_UNAL_SUPPORTED); 150 151 ddr2->rtr = 0x2b0; 152 153 ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | 154 3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | 155 3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | 156 10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | 157 3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | 158 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | 159 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | 160 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); 161 162 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | 163 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | 164 25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | 165 23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); 166 167 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | 168 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | 169 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | 170 2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | 171 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); 172 } 173 174 void mem_init(void) 175 { 176 struct atmel_mpddrc_config ddr2; 177 const struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; 178 u32 tmp; 179 180 ddr2_conf(&ddr2); 181 182 /* Enable MPDDR clock */ 183 at91_periph_clk_enable(ATMEL_ID_MPDDRC); 184 at91_system_clk_enable(AT91_PMC_DDR); 185 186 tmp = ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE; 187 writel(tmp, &mpddr->rd_data_path); 188 189 tmp = readl(&mpddr->io_calibr); 190 tmp = (tmp & ~(ATMEL_MPDDRC_IO_CALIBR_RDIV | 191 ATMEL_MPDDRC_IO_CALIBR_TZQIO | 192 ATMEL_MPDDRC_IO_CALIBR_CALCODEP | 193 ATMEL_MPDDRC_IO_CALIBR_CALCODEN)) | 194 ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_52 | 195 ATMEL_MPDDRC_IO_CALIBR_TZQIO_(8) | 196 ATMEL_MPDDRC_IO_CALIBR_EN_CALIB; 197 writel(tmp, &mpddr->io_calibr); 198 199 /* DDRAM2 Controller initialize */ 200 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); 201 } 202 203 void at91_pmc_init(void) 204 { 205 u32 tmp; 206 207 tmp = AT91_PMC_PLLAR_29 | 208 AT91_PMC_PLLXR_PLLCOUNT(0x3f) | 209 AT91_PMC_PLLXR_MUL(87) | 210 AT91_PMC_PLLXR_DIV(1); 211 at91_plla_init(tmp); 212 213 at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x0)); 214 215 tmp = AT91_PMC_MCKR_H32MXDIV | 216 AT91_PMC_MCKR_PLLADIV_2 | 217 AT91_PMC_MCKR_MDIV_3 | 218 AT91_PMC_MCKR_CSS_PLLA; 219 at91_mck_init(tmp); 220 } 221 #endif 222