1 /* 2 * Copyright (C) 2014 Atmel 3 * Bo Shen <voice.shen@atmel.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <asm/arch/at91_common.h> 11 #include <asm/arch/at91_pmc.h> 12 #include <asm/arch/at91_rstc.h> 13 #include <asm/arch/atmel_mpddrc.h> 14 #include <asm/arch/atmel_usba_udc.h> 15 #include <asm/arch/gpio.h> 16 #include <asm/arch/clk.h> 17 #include <asm/arch/sama5d3_smc.h> 18 #include <asm/arch/sama5d4.h> 19 #include <atmel_hlcdc.h> 20 #include <atmel_mci.h> 21 #include <lcd.h> 22 #include <mmc.h> 23 #include <net.h> 24 #include <netdev.h> 25 #include <nand.h> 26 #include <spi.h> 27 #include <version.h> 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 #ifdef CONFIG_ATMEL_SPI 32 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 33 { 34 return bus == 0 && cs == 0; 35 } 36 37 void spi_cs_activate(struct spi_slave *slave) 38 { 39 at91_set_pio_output(AT91_PIO_PORTC, 3, 0); 40 } 41 42 void spi_cs_deactivate(struct spi_slave *slave) 43 { 44 at91_set_pio_output(AT91_PIO_PORTC, 3, 1); 45 } 46 47 static void sama5d4ek_spi0_hw_init(void) 48 { 49 at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */ 50 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */ 51 at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */ 52 53 at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */ 54 55 /* Enable clock */ 56 at91_periph_clk_enable(ATMEL_ID_SPI0); 57 } 58 #endif /* CONFIG_ATMEL_SPI */ 59 60 #ifdef CONFIG_NAND_ATMEL 61 static void sama5d4ek_nand_hw_init(void) 62 { 63 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 64 65 at91_periph_clk_enable(ATMEL_ID_SMC); 66 67 /* Configure SMC CS3 for NAND */ 68 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | 69 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1), 70 &smc->cs[3].setup); 71 writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) | 72 AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3), 73 &smc->cs[3].pulse); 74 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), 75 &smc->cs[3].cycle); 76 writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) | 77 AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) | 78 AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3)| 79 AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); 80 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 81 AT91_SMC_MODE_EXNW_DISABLE | 82 AT91_SMC_MODE_DBW_8 | 83 AT91_SMC_MODE_TDF_CYCLE(3), 84 &smc->cs[3].mode); 85 86 at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */ 87 at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */ 88 at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */ 89 at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */ 90 at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */ 91 at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */ 92 at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */ 93 at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */ 94 at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */ 95 at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */ 96 at91_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */ 97 at91_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */ 98 at91_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */ 99 at91_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */ 100 } 101 #endif 102 103 #ifdef CONFIG_CMD_USB 104 static void sama5d4ek_usb_hw_init(void) 105 { 106 at91_set_pio_output(AT91_PIO_PORTE, 11, 0); 107 at91_set_pio_output(AT91_PIO_PORTE, 12, 0); 108 at91_set_pio_output(AT91_PIO_PORTE, 10, 0); 109 } 110 #endif 111 112 #ifdef CONFIG_LCD 113 vidinfo_t panel_info = { 114 .vl_col = 800, 115 .vl_row = 480, 116 .vl_clk = 33260000, 117 .vl_bpix = LCD_BPP, 118 .vl_tft = 1, 119 .vl_hsync_len = 5, 120 .vl_left_margin = 128, 121 .vl_right_margin = 0, 122 .vl_vsync_len = 5, 123 .vl_upper_margin = 23, 124 .vl_lower_margin = 22, 125 .mmio = ATMEL_BASE_LCDC, 126 }; 127 128 /* No power up/down pin for the LCD pannel */ 129 void lcd_enable(void) { /* Empty! */ } 130 void lcd_disable(void) { /* Empty! */ } 131 132 unsigned int has_lcdc(void) 133 { 134 return 1; 135 } 136 137 static void sama5d4ek_lcd_hw_init(void) 138 { 139 at91_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */ 140 at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */ 141 at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */ 142 at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */ 143 at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */ 144 at91_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */ 145 146 at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */ 147 at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */ 148 at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */ 149 at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */ 150 at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */ 151 at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */ 152 153 at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */ 154 at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */ 155 at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */ 156 at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */ 157 at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */ 158 at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */ 159 160 at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */ 161 at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */ 162 at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */ 163 at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */ 164 at91_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */ 165 at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */ 166 167 /* Enable clock */ 168 at91_periph_clk_enable(ATMEL_ID_LCDC); 169 } 170 171 #ifdef CONFIG_LCD_INFO 172 void lcd_show_board_info(void) 173 { 174 ulong dram_size, nand_size; 175 int i; 176 char temp[32]; 177 178 lcd_printf("%s\n", U_BOOT_VERSION); 179 lcd_printf("2014 ATMEL Corp\n"); 180 lcd_printf("at91@atmel.com\n"); 181 lcd_printf("%s CPU at %s MHz\n", get_cpu_name(), 182 strmhz(temp, get_cpu_clk_rate())); 183 184 dram_size = 0; 185 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 186 dram_size += gd->bd->bi_dram[i].size; 187 188 nand_size = 0; 189 #ifdef CONFIG_NAND_ATMEL 190 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 191 nand_size += nand_info[i].size; 192 #endif 193 lcd_printf("%ld MB SDRAM, %ld MB NAND\n", 194 dram_size >> 20, nand_size >> 20); 195 } 196 #endif /* CONFIG_LCD_INFO */ 197 198 #endif /* CONFIG_LCD */ 199 200 #ifdef CONFIG_GENERIC_ATMEL_MCI 201 void sama5d4ek_mci1_hw_init(void) 202 { 203 at91_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */ 204 at91_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */ 205 at91_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */ 206 at91_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */ 207 at91_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */ 208 at91_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */ 209 210 /* 211 * As the mci io internal pull down is too strong, so if the io needs 212 * external pull up, the pull up resistor will be very small, if so 213 * the power consumption will increase, so disable the interanl pull 214 * down to save the power. 215 */ 216 at91_set_pio_pulldown(AT91_PIO_PORTE, 18, 0); 217 at91_set_pio_pulldown(AT91_PIO_PORTE, 19, 0); 218 at91_set_pio_pulldown(AT91_PIO_PORTE, 20, 0); 219 at91_set_pio_pulldown(AT91_PIO_PORTE, 21, 0); 220 at91_set_pio_pulldown(AT91_PIO_PORTE, 22, 0); 221 at91_set_pio_pulldown(AT91_PIO_PORTE, 23, 0); 222 223 /* Enable clock */ 224 at91_periph_clk_enable(ATMEL_ID_MCI1); 225 } 226 227 int board_mmc_init(bd_t *bis) 228 { 229 /* Enable power for MCI1 interface */ 230 at91_set_pio_output(AT91_PIO_PORTE, 15, 0); 231 232 return atmel_mci_init((void *)ATMEL_BASE_MCI1); 233 } 234 #endif /* CONFIG_GENERIC_ATMEL_MCI */ 235 236 #ifdef CONFIG_MACB 237 void sama5d4ek_macb0_hw_init(void) 238 { 239 at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */ 240 at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */ 241 at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */ 242 at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */ 243 at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */ 244 at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */ 245 at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */ 246 at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */ 247 at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */ 248 at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */ 249 250 /* Enable clock */ 251 at91_periph_clk_enable(ATMEL_ID_GMAC0); 252 } 253 #endif 254 255 static void sama5d4ek_serial3_hw_init(void) 256 { 257 at91_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */ 258 at91_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */ 259 260 /* Enable clock */ 261 at91_periph_clk_enable(ATMEL_ID_USART3); 262 } 263 264 int board_early_init_f(void) 265 { 266 at91_periph_clk_enable(ATMEL_ID_PIOA); 267 at91_periph_clk_enable(ATMEL_ID_PIOB); 268 at91_periph_clk_enable(ATMEL_ID_PIOC); 269 at91_periph_clk_enable(ATMEL_ID_PIOD); 270 at91_periph_clk_enable(ATMEL_ID_PIOE); 271 272 sama5d4ek_serial3_hw_init(); 273 274 return 0; 275 } 276 277 int board_init(void) 278 { 279 /* adress of boot parameters */ 280 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 281 282 #ifdef CONFIG_ATMEL_SPI 283 sama5d4ek_spi0_hw_init(); 284 #endif 285 #ifdef CONFIG_NAND_ATMEL 286 sama5d4ek_nand_hw_init(); 287 #endif 288 #ifdef CONFIG_GENERIC_ATMEL_MCI 289 sama5d4ek_mci1_hw_init(); 290 #endif 291 #ifdef CONFIG_MACB 292 sama5d4ek_macb0_hw_init(); 293 #endif 294 #ifdef CONFIG_LCD 295 sama5d4ek_lcd_hw_init(); 296 #endif 297 #ifdef CONFIG_CMD_USB 298 sama5d4ek_usb_hw_init(); 299 #endif 300 #ifdef CONFIG_USB_GADGET_ATMEL_USBA 301 at91_udp_hw_init(); 302 #endif 303 304 return 0; 305 } 306 307 int dram_init(void) 308 { 309 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 310 CONFIG_SYS_SDRAM_SIZE); 311 return 0; 312 } 313 314 int board_eth_init(bd_t *bis) 315 { 316 int rc = 0; 317 318 #ifdef CONFIG_MACB 319 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00); 320 #endif 321 322 #ifdef CONFIG_USB_GADGET_ATMEL_USBA 323 usba_udc_probe(&pdata); 324 #ifdef CONFIG_USB_ETH_RNDIS 325 usb_eth_initialize(bis); 326 #endif 327 #endif 328 329 return rc; 330 } 331 332 /* SPL */ 333 #ifdef CONFIG_SPL_BUILD 334 void spl_board_init(void) 335 { 336 #ifdef CONFIG_SYS_USE_MMC 337 sama5d4ek_mci1_hw_init(); 338 #elif CONFIG_SYS_USE_NANDFLASH 339 sama5d4ek_nand_hw_init(); 340 #elif CONFIG_SYS_USE_SERIALFLASH 341 sama5d4ek_spi0_hw_init(); 342 #endif 343 } 344 345 static void ddr2_conf(struct atmel_mpddr *ddr2) 346 { 347 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); 348 349 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | 350 ATMEL_MPDDRC_CR_NR_ROW_14 | 351 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | 352 ATMEL_MPDDRC_CR_NB_8BANKS | 353 ATMEL_MPDDRC_CR_NDQS_DISABLED | 354 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | 355 ATMEL_MPDDRC_CR_UNAL_SUPPORTED); 356 357 ddr2->rtr = 0x2b0; 358 359 ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | 360 3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | 361 3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | 362 10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | 363 3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | 364 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | 365 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | 366 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); 367 368 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | 369 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | 370 25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | 371 23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); 372 373 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | 374 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | 375 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | 376 2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | 377 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); 378 } 379 380 void mem_init(void) 381 { 382 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 383 struct atmel_mpddr ddr2; 384 385 ddr2_conf(&ddr2); 386 387 /* enable MPDDR clock */ 388 at91_periph_clk_enable(ATMEL_ID_MPDDRC); 389 writel(AT91_PMC_DDR, &pmc->scer); 390 391 /* DDRAM2 Controller initialize */ 392 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); 393 } 394 395 void at91_pmc_init(void) 396 { 397 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 398 u32 tmp; 399 400 tmp = AT91_PMC_PLLAR_29 | 401 AT91_PMC_PLLXR_PLLCOUNT(0x3f) | 402 AT91_PMC_PLLXR_MUL(87) | 403 AT91_PMC_PLLXR_DIV(1); 404 at91_plla_init(tmp); 405 406 writel(0x0 << 8, &pmc->pllicpr); 407 408 tmp = AT91_PMC_MCKR_H32MXDIV | 409 AT91_PMC_MCKR_PLLADIV_2 | 410 AT91_PMC_MCKR_MDIV_3 | 411 AT91_PMC_MCKR_CSS_PLLA; 412 at91_mck_init(tmp); 413 } 414 #endif 415