1 /* 2 * Copyright (C) 2014 Atmel 3 * Bo Shen <voice.shen@atmel.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <asm/arch/at91_common.h> 11 #include <asm/arch/at91_pmc.h> 12 #include <asm/arch/at91_rstc.h> 13 #include <asm/arch/atmel_usba_udc.h> 14 #include <asm/arch/gpio.h> 15 #include <asm/arch/clk.h> 16 #include <asm/arch/sama5d3_smc.h> 17 #include <asm/arch/sama5d4.h> 18 #include <atmel_hlcdc.h> 19 #include <atmel_mci.h> 20 #include <lcd.h> 21 #include <mmc.h> 22 #include <net.h> 23 #include <netdev.h> 24 #include <nand.h> 25 #include <spi.h> 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 #ifdef CONFIG_ATMEL_SPI 30 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 31 { 32 return bus == 0 && cs == 0; 33 } 34 35 void spi_cs_activate(struct spi_slave *slave) 36 { 37 at91_set_pio_output(AT91_PIO_PORTC, 3, 0); 38 } 39 40 void spi_cs_deactivate(struct spi_slave *slave) 41 { 42 at91_set_pio_output(AT91_PIO_PORTC, 3, 1); 43 } 44 45 static void sama5d4ek_spi0_hw_init(void) 46 { 47 at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */ 48 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */ 49 at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */ 50 51 at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */ 52 53 /* Enable clock */ 54 at91_periph_clk_enable(ATMEL_ID_SPI0); 55 } 56 #endif /* CONFIG_ATMEL_SPI */ 57 58 #ifdef CONFIG_NAND_ATMEL 59 static void sama5d4ek_nand_hw_init(void) 60 { 61 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 62 63 at91_periph_clk_enable(ATMEL_ID_SMC); 64 65 /* Configure SMC CS3 for NAND */ 66 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | 67 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1), 68 &smc->cs[3].setup); 69 writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) | 70 AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3), 71 &smc->cs[3].pulse); 72 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), 73 &smc->cs[3].cycle); 74 writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) | 75 AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) | 76 AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3)| 77 AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); 78 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 79 AT91_SMC_MODE_EXNW_DISABLE | 80 AT91_SMC_MODE_DBW_8 | 81 AT91_SMC_MODE_TDF_CYCLE(3), 82 &smc->cs[3].mode); 83 84 at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */ 85 at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */ 86 at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */ 87 at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */ 88 at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */ 89 at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */ 90 at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */ 91 at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */ 92 at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */ 93 at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */ 94 at91_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */ 95 at91_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */ 96 at91_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */ 97 at91_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */ 98 } 99 #endif 100 101 #ifdef CONFIG_CMD_USB 102 static void sama5d4ek_usb_hw_init(void) 103 { 104 at91_set_pio_output(AT91_PIO_PORTE, 11, 0); 105 at91_set_pio_output(AT91_PIO_PORTE, 12, 0); 106 at91_set_pio_output(AT91_PIO_PORTE, 10, 0); 107 } 108 #endif 109 110 #ifdef CONFIG_LCD 111 vidinfo_t panel_info = { 112 .vl_col = 800, 113 .vl_row = 480, 114 .vl_clk = 33260000, 115 .vl_bpix = LCD_BPP, 116 .vl_tft = 1, 117 .vl_hsync_len = 5, 118 .vl_left_margin = 128, 119 .vl_right_margin = 0, 120 .vl_vsync_len = 5, 121 .vl_upper_margin = 23, 122 .vl_lower_margin = 22, 123 .mmio = ATMEL_BASE_LCDC, 124 }; 125 126 /* No power up/down pin for the LCD pannel */ 127 void lcd_enable(void) { /* Empty! */ } 128 void lcd_disable(void) { /* Empty! */ } 129 130 unsigned int has_lcdc(void) 131 { 132 return 1; 133 } 134 135 static void sama5d4ek_lcd_hw_init(void) 136 { 137 at91_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */ 138 at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */ 139 at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */ 140 at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */ 141 at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */ 142 at91_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */ 143 144 at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */ 145 at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */ 146 at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */ 147 at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */ 148 at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */ 149 at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */ 150 151 at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */ 152 at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */ 153 at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */ 154 at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */ 155 at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */ 156 at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */ 157 158 at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */ 159 at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */ 160 at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */ 161 at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */ 162 at91_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */ 163 at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */ 164 165 /* Enable clock */ 166 at91_periph_clk_enable(ATMEL_ID_LCDC); 167 } 168 169 #ifdef CONFIG_LCD_INFO 170 void lcd_show_board_info(void) 171 { 172 ulong dram_size, nand_size; 173 int i; 174 char temp[32]; 175 176 lcd_printf("2014 ATMEL Corp\n"); 177 lcd_printf("at91@atmel.com\n"); 178 lcd_printf("%s CPU at %s MHz\n", get_cpu_name(), 179 strmhz(temp, get_cpu_clk_rate())); 180 181 dram_size = 0; 182 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 183 dram_size += gd->bd->bi_dram[i].size; 184 185 nand_size = 0; 186 #ifdef CONFIG_NAND_ATMEL 187 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 188 nand_size += nand_info[i].size; 189 #endif 190 lcd_printf("%ld MB SDRAM, %ld MB NAND\n", 191 dram_size >> 20, nand_size >> 20); 192 } 193 #endif /* CONFIG_LCD_INFO */ 194 195 #endif /* CONFIG_LCD */ 196 197 #ifdef CONFIG_GENERIC_ATMEL_MCI 198 void sama5d4ek_mci1_hw_init(void) 199 { 200 at91_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */ 201 at91_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */ 202 at91_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */ 203 at91_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */ 204 at91_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */ 205 at91_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */ 206 207 /* 208 * As the mci io internal pull down is too strong, so if the io needs 209 * external pull up, the pull up resistor will be very small, if so 210 * the power consumption will increase, so disable the interanl pull 211 * down to save the power. 212 */ 213 at91_set_pio_pulldown(AT91_PIO_PORTE, 18, 0); 214 at91_set_pio_pulldown(AT91_PIO_PORTE, 19, 0); 215 at91_set_pio_pulldown(AT91_PIO_PORTE, 20, 0); 216 at91_set_pio_pulldown(AT91_PIO_PORTE, 21, 0); 217 at91_set_pio_pulldown(AT91_PIO_PORTE, 22, 0); 218 at91_set_pio_pulldown(AT91_PIO_PORTE, 23, 0); 219 220 /* Enable clock */ 221 at91_periph_clk_enable(ATMEL_ID_MCI1); 222 } 223 224 int board_mmc_init(bd_t *bis) 225 { 226 /* Enable power for MCI1 interface */ 227 at91_set_pio_output(AT91_PIO_PORTE, 15, 0); 228 229 return atmel_mci_init((void *)ATMEL_BASE_MCI1); 230 } 231 #endif /* CONFIG_GENERIC_ATMEL_MCI */ 232 233 #ifdef CONFIG_MACB 234 void sama5d4ek_macb0_hw_init(void) 235 { 236 at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */ 237 at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */ 238 at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */ 239 at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */ 240 at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */ 241 at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */ 242 at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */ 243 at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */ 244 at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */ 245 at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */ 246 247 /* Enable clock */ 248 at91_periph_clk_enable(ATMEL_ID_GMAC0); 249 } 250 #endif 251 252 static void sama5d4ek_serial3_hw_init(void) 253 { 254 at91_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */ 255 at91_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */ 256 257 /* Enable clock */ 258 at91_periph_clk_enable(ATMEL_ID_USART3); 259 } 260 261 int board_early_init_f(void) 262 { 263 at91_periph_clk_enable(ATMEL_ID_PIOA); 264 at91_periph_clk_enable(ATMEL_ID_PIOB); 265 at91_periph_clk_enable(ATMEL_ID_PIOC); 266 at91_periph_clk_enable(ATMEL_ID_PIOD); 267 at91_periph_clk_enable(ATMEL_ID_PIOE); 268 269 sama5d4ek_serial3_hw_init(); 270 271 return 0; 272 } 273 274 int board_init(void) 275 { 276 /* adress of boot parameters */ 277 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 278 279 #ifdef CONFIG_ATMEL_SPI 280 sama5d4ek_spi0_hw_init(); 281 #endif 282 #ifdef CONFIG_NAND_ATMEL 283 sama5d4ek_nand_hw_init(); 284 #endif 285 #ifdef CONFIG_GENERIC_ATMEL_MCI 286 sama5d4ek_mci1_hw_init(); 287 #endif 288 #ifdef CONFIG_MACB 289 sama5d4ek_macb0_hw_init(); 290 #endif 291 #ifdef CONFIG_LCD 292 sama5d4ek_lcd_hw_init(); 293 #endif 294 #ifdef CONFIG_CMD_USB 295 sama5d4ek_usb_hw_init(); 296 #endif 297 #ifdef CONFIG_USB_GADGET_ATMEL_USBA 298 at91_udp_hw_init(); 299 #endif 300 301 return 0; 302 } 303 304 int dram_init(void) 305 { 306 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 307 CONFIG_SYS_SDRAM_SIZE); 308 return 0; 309 } 310 311 int board_eth_init(bd_t *bis) 312 { 313 int rc = 0; 314 315 #ifdef CONFIG_MACB 316 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00); 317 #endif 318 319 #ifdef CONFIG_USB_GADGET_ATMEL_USBA 320 usba_udc_probe(&pdata); 321 #ifdef CONFIG_USB_ETH_RNDIS 322 usb_eth_initialize(bis); 323 #endif 324 #endif 325 326 return rc; 327 } 328