1 /* 2 * Copyright (C) 2014 Atmel 3 * Bo Shen <voice.shen@atmel.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <asm/arch/at91_common.h> 11 #include <asm/arch/at91_pmc.h> 12 #include <asm/arch/at91_rstc.h> 13 #include <asm/arch/atmel_usba_udc.h> 14 #include <asm/arch/gpio.h> 15 #include <asm/arch/clk.h> 16 #include <asm/arch/sama5d3_smc.h> 17 #include <asm/arch/sama5d4.h> 18 #include <atmel_hlcdc.h> 19 #include <atmel_mci.h> 20 #include <lcd.h> 21 #include <mmc.h> 22 #include <net.h> 23 #include <netdev.h> 24 #include <nand.h> 25 #include <spi.h> 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 #ifdef CONFIG_ATMEL_SPI 30 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 31 { 32 return bus == 0 && cs == 0; 33 } 34 35 void spi_cs_activate(struct spi_slave *slave) 36 { 37 at91_set_pio_output(AT91_PIO_PORTC, 3, 0); 38 } 39 40 void spi_cs_deactivate(struct spi_slave *slave) 41 { 42 at91_set_pio_output(AT91_PIO_PORTC, 3, 1); 43 } 44 45 static void sama5d4_xplained_spi0_hw_init(void) 46 { 47 at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */ 48 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */ 49 at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */ 50 51 at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */ 52 53 /* Enable clock */ 54 at91_periph_clk_enable(ATMEL_ID_SPI0); 55 } 56 #endif /* CONFIG_ATMEL_SPI */ 57 58 #ifdef CONFIG_NAND_ATMEL 59 static void sama5d4_xplained_nand_hw_init(void) 60 { 61 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 62 63 at91_periph_clk_enable(ATMEL_ID_SMC); 64 65 /* Configure SMC CS3 for NAND */ 66 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | 67 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1), 68 &smc->cs[3].setup); 69 writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) | 70 AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3), 71 &smc->cs[3].pulse); 72 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), 73 &smc->cs[3].cycle); 74 writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) | 75 AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) | 76 AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3)| 77 AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); 78 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 79 AT91_SMC_MODE_EXNW_DISABLE | 80 AT91_SMC_MODE_DBW_8 | 81 AT91_SMC_MODE_TDF_CYCLE(3), 82 &smc->cs[3].mode); 83 84 at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */ 85 at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */ 86 at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */ 87 at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */ 88 at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */ 89 at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */ 90 at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */ 91 at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */ 92 at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */ 93 at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */ 94 at91_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */ 95 at91_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */ 96 at91_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */ 97 at91_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */ 98 } 99 #endif 100 101 #ifdef CONFIG_CMD_USB 102 static void sama5d4_xplained_usb_hw_init(void) 103 { 104 at91_set_pio_output(AT91_PIO_PORTE, 11, 1); 105 at91_set_pio_output(AT91_PIO_PORTE, 14, 1); 106 } 107 #endif 108 109 #ifdef CONFIG_LCD 110 vidinfo_t panel_info = { 111 .vl_col = 480, 112 .vl_row = 272, 113 .vl_clk = 9000000, 114 .vl_bpix = LCD_BPP, 115 .vl_tft = 1, 116 .vl_hsync_len = 41, 117 .vl_left_margin = 2, 118 .vl_right_margin = 2, 119 .vl_vsync_len = 11, 120 .vl_upper_margin = 2, 121 .vl_lower_margin = 2, 122 .mmio = ATMEL_BASE_LCDC, 123 }; 124 125 /* No power up/down pin for the LCD pannel */ 126 void lcd_enable(void) { /* Empty! */ } 127 void lcd_disable(void) { /* Empty! */ } 128 129 unsigned int has_lcdc(void) 130 { 131 return 1; 132 } 133 134 static void sama5d4_xplained_lcd_hw_init(void) 135 { 136 at91_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */ 137 at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */ 138 at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */ 139 at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */ 140 at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */ 141 at91_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */ 142 143 at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */ 144 at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */ 145 at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */ 146 at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */ 147 at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */ 148 at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */ 149 at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */ 150 at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */ 151 152 at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD9 */ 153 at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD8 */ 154 at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */ 155 at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */ 156 at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */ 157 at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */ 158 at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */ 159 at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */ 160 161 at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* LCDD16 */ 162 at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* LCDD17 */ 163 at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */ 164 at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */ 165 at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */ 166 at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */ 167 at91_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */ 168 at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */ 169 170 /* Enable clock */ 171 at91_periph_clk_enable(ATMEL_ID_LCDC); 172 } 173 174 #ifdef CONFIG_LCD_INFO 175 void lcd_show_board_info(void) 176 { 177 ulong dram_size, nand_size; 178 int i; 179 char temp[32]; 180 181 lcd_printf("2014 ATMEL Corp\n"); 182 lcd_printf("%s CPU at %s MHz\n", get_cpu_name(), 183 strmhz(temp, get_cpu_clk_rate())); 184 185 dram_size = 0; 186 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 187 dram_size += gd->bd->bi_dram[i].size; 188 189 nand_size = 0; 190 #ifdef CONFIG_NAND_ATMEL 191 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 192 nand_size += nand_info[i].size; 193 #endif 194 lcd_printf("%ld MB SDRAM, %ld MB NAND\n", 195 dram_size >> 20, nand_size >> 20); 196 } 197 #endif /* CONFIG_LCD_INFO */ 198 199 #endif /* CONFIG_LCD */ 200 201 #ifdef CONFIG_GENERIC_ATMEL_MCI 202 void sama5d4_xplained_mci1_hw_init(void) 203 { 204 at91_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */ 205 at91_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */ 206 at91_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */ 207 at91_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */ 208 at91_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */ 209 at91_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */ 210 211 /* 212 * As the mci io internal pull down is too strong, so if the io needs 213 * external pull up, the pull up resistor will be very small, if so 214 * the power consumption will increase, so disable the interanl pull 215 * down to save the power. 216 */ 217 at91_set_pio_pulldown(AT91_PIO_PORTE, 18, 0); 218 at91_set_pio_pulldown(AT91_PIO_PORTE, 19, 0); 219 at91_set_pio_pulldown(AT91_PIO_PORTE, 20, 0); 220 at91_set_pio_pulldown(AT91_PIO_PORTE, 21, 0); 221 at91_set_pio_pulldown(AT91_PIO_PORTE, 22, 0); 222 at91_set_pio_pulldown(AT91_PIO_PORTE, 23, 0); 223 224 /* Enable clock */ 225 at91_periph_clk_enable(ATMEL_ID_MCI1); 226 } 227 228 int board_mmc_init(bd_t *bis) 229 { 230 return atmel_mci_init((void *)ATMEL_BASE_MCI1); 231 } 232 #endif /* CONFIG_GENERIC_ATMEL_MCI */ 233 234 #ifdef CONFIG_MACB 235 void sama5d4_xplained_macb0_hw_init(void) 236 { 237 at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */ 238 at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */ 239 at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */ 240 at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */ 241 at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */ 242 at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */ 243 at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */ 244 at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */ 245 at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */ 246 at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */ 247 248 /* Enable clock */ 249 at91_periph_clk_enable(ATMEL_ID_GMAC0); 250 } 251 #endif 252 253 static void sama5d4_xplained_serial3_hw_init(void) 254 { 255 at91_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */ 256 at91_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */ 257 258 /* Enable clock */ 259 at91_periph_clk_enable(ATMEL_ID_USART3); 260 } 261 262 int board_early_init_f(void) 263 { 264 at91_periph_clk_enable(ATMEL_ID_PIOA); 265 at91_periph_clk_enable(ATMEL_ID_PIOB); 266 at91_periph_clk_enable(ATMEL_ID_PIOC); 267 at91_periph_clk_enable(ATMEL_ID_PIOD); 268 at91_periph_clk_enable(ATMEL_ID_PIOE); 269 270 sama5d4_xplained_serial3_hw_init(); 271 272 return 0; 273 } 274 275 int board_init(void) 276 { 277 /* adress of boot parameters */ 278 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 279 280 #ifdef CONFIG_ATMEL_SPI 281 sama5d4_xplained_spi0_hw_init(); 282 #endif 283 #ifdef CONFIG_NAND_ATMEL 284 sama5d4_xplained_nand_hw_init(); 285 #endif 286 #ifdef CONFIG_GENERIC_ATMEL_MCI 287 sama5d4_xplained_mci1_hw_init(); 288 #endif 289 #ifdef CONFIG_MACB 290 sama5d4_xplained_macb0_hw_init(); 291 #endif 292 #ifdef CONFIG_LCD 293 sama5d4_xplained_lcd_hw_init(); 294 #endif 295 #ifdef CONFIG_CMD_USB 296 sama5d4_xplained_usb_hw_init(); 297 #endif 298 #ifdef CONFIG_USB_GADGET_ATMEL_USBA 299 at91_udp_hw_init(); 300 #endif 301 302 return 0; 303 } 304 305 int dram_init(void) 306 { 307 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 308 CONFIG_SYS_SDRAM_SIZE); 309 return 0; 310 } 311 312 int board_eth_init(bd_t *bis) 313 { 314 int rc = 0; 315 316 #ifdef CONFIG_MACB 317 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00); 318 #endif 319 320 #ifdef CONFIG_USB_GADGET_ATMEL_USBA 321 usba_udc_probe(&pdata); 322 #ifdef CONFIG_USB_ETH_RNDIS 323 usb_eth_initialize(bis); 324 #endif 325 #endif 326 327 return rc; 328 } 329