1 /* 2 * Copyright (C) 2014 Atmel 3 * Bo Shen <voice.shen@atmel.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <asm/arch/at91_common.h> 11 #include <asm/arch/at91_pmc.h> 12 #include <asm/arch/at91_rstc.h> 13 #include <asm/arch/gpio.h> 14 #include <asm/arch/clk.h> 15 #include <asm/arch/sama5d3_smc.h> 16 #include <asm/arch/sama5d4.h> 17 #include <atmel_lcdc.h> 18 #include <atmel_mci.h> 19 #include <lcd.h> 20 #include <mmc.h> 21 #include <net.h> 22 #include <netdev.h> 23 #include <nand.h> 24 #include <spi.h> 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 #ifdef CONFIG_ATMEL_SPI 29 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 30 { 31 return bus == 0 && cs == 0; 32 } 33 34 void spi_cs_activate(struct spi_slave *slave) 35 { 36 at91_set_pio_output(AT91_PIO_PORTC, 3, 0); 37 } 38 39 void spi_cs_deactivate(struct spi_slave *slave) 40 { 41 at91_set_pio_output(AT91_PIO_PORTC, 3, 1); 42 } 43 44 static void sama5d4_xplained_spi0_hw_init(void) 45 { 46 at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */ 47 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */ 48 at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */ 49 50 at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */ 51 52 /* Enable clock */ 53 at91_periph_clk_enable(ATMEL_ID_SPI0); 54 } 55 #endif /* CONFIG_ATMEL_SPI */ 56 57 #ifdef CONFIG_NAND_ATMEL 58 static void sama5d4_xplained_nand_hw_init(void) 59 { 60 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 61 62 at91_periph_clk_enable(ATMEL_ID_SMC); 63 64 /* Configure SMC CS3 for NAND */ 65 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | 66 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1), 67 &smc->cs[3].setup); 68 writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) | 69 AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3), 70 &smc->cs[3].pulse); 71 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), 72 &smc->cs[3].cycle); 73 writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) | 74 AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) | 75 AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3)| 76 AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); 77 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 78 AT91_SMC_MODE_EXNW_DISABLE | 79 AT91_SMC_MODE_DBW_8 | 80 AT91_SMC_MODE_TDF_CYCLE(3), 81 &smc->cs[3].mode); 82 83 at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */ 84 at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */ 85 at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */ 86 at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */ 87 at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */ 88 at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */ 89 at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */ 90 at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */ 91 at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */ 92 at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */ 93 at91_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */ 94 at91_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */ 95 at91_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */ 96 at91_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */ 97 } 98 #endif 99 100 #ifdef CONFIG_CMD_USB 101 static void sama5d4_xplained_usb_hw_init(void) 102 { 103 at91_set_pio_output(AT91_PIO_PORTE, 11, 1); 104 at91_set_pio_output(AT91_PIO_PORTE, 14, 1); 105 } 106 #endif 107 108 #ifdef CONFIG_LCD 109 vidinfo_t panel_info = { 110 .vl_col = 480, 111 .vl_row = 272, 112 .vl_clk = 9000, 113 .vl_sync = ATMEL_LCDC_INVLINE_NORMAL | ATMEL_LCDC_INVFRAME_NORMAL, 114 .vl_bpix = LCD_BPP, 115 .vl_bpox = LCD_OUTPUT_BPP, 116 .vl_tft = 1, 117 .vl_hsync_len = 41, 118 .vl_left_margin = 2, 119 .vl_right_margin = 2, 120 .vl_vsync_len = 11, 121 .vl_upper_margin = 2, 122 .vl_lower_margin = 2, 123 .mmio = ATMEL_BASE_LCDC, 124 }; 125 126 /* No power up/down pin for the LCD pannel */ 127 void lcd_enable(void) { /* Empty! */ } 128 void lcd_disable(void) { /* Empty! */ } 129 130 unsigned int has_lcdc(void) 131 { 132 return 1; 133 } 134 135 static void sama5d4_xplained_lcd_hw_init(void) 136 { 137 at91_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */ 138 at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */ 139 at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */ 140 at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */ 141 at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */ 142 at91_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */ 143 144 at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */ 145 at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */ 146 at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */ 147 at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */ 148 at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */ 149 at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */ 150 at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */ 151 at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */ 152 153 at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD9 */ 154 at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD8 */ 155 at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */ 156 at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */ 157 at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */ 158 at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */ 159 at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */ 160 at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */ 161 162 at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* LCDD16 */ 163 at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* LCDD17 */ 164 at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */ 165 at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */ 166 at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */ 167 at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */ 168 at91_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */ 169 at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */ 170 171 /* Enable clock */ 172 at91_periph_clk_enable(ATMEL_ID_LCDC); 173 } 174 175 #ifdef CONFIG_LCD_INFO 176 void lcd_show_board_info(void) 177 { 178 ulong dram_size, nand_size; 179 int i; 180 char temp[32]; 181 182 lcd_printf("2014 ATMEL Corp\n"); 183 lcd_printf("%s CPU at %s MHz\n", get_cpu_name(), 184 strmhz(temp, get_cpu_clk_rate())); 185 186 dram_size = 0; 187 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 188 dram_size += gd->bd->bi_dram[i].size; 189 190 nand_size = 0; 191 #ifdef CONFIG_NAND_ATMEL 192 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 193 nand_size += nand_info[i].size; 194 #endif 195 lcd_printf("%ld MB SDRAM, %ld MB NAND\n", 196 dram_size >> 20, nand_size >> 20); 197 } 198 #endif /* CONFIG_LCD_INFO */ 199 200 #endif /* CONFIG_LCD */ 201 202 #ifdef CONFIG_GENERIC_ATMEL_MCI 203 void sama5d4_xplained_mci1_hw_init(void) 204 { 205 at91_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */ 206 at91_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */ 207 at91_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */ 208 at91_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */ 209 at91_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */ 210 at91_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */ 211 212 /* 213 * As the mci io internal pull down is too strong, so if the io needs 214 * external pull up, the pull up resistor will be very small, if so 215 * the power consumption will increase, so disable the interanl pull 216 * down to save the power. 217 */ 218 at91_set_pio_pulldown(AT91_PIO_PORTE, 18, 0); 219 at91_set_pio_pulldown(AT91_PIO_PORTE, 19, 0); 220 at91_set_pio_pulldown(AT91_PIO_PORTE, 20, 0); 221 at91_set_pio_pulldown(AT91_PIO_PORTE, 21, 0); 222 at91_set_pio_pulldown(AT91_PIO_PORTE, 22, 0); 223 at91_set_pio_pulldown(AT91_PIO_PORTE, 23, 0); 224 225 /* Enable clock */ 226 at91_periph_clk_enable(ATMEL_ID_MCI1); 227 } 228 229 int board_mmc_init(bd_t *bis) 230 { 231 return atmel_mci_init((void *)ATMEL_BASE_MCI1); 232 } 233 #endif /* CONFIG_GENERIC_ATMEL_MCI */ 234 235 #ifdef CONFIG_MACB 236 void sama5d4_xplained_macb0_hw_init(void) 237 { 238 at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */ 239 at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */ 240 at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */ 241 at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */ 242 at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */ 243 at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */ 244 at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */ 245 at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */ 246 at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */ 247 at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */ 248 249 /* Enable clock */ 250 at91_periph_clk_enable(ATMEL_ID_GMAC0); 251 } 252 #endif 253 254 static void sama5d4_xplained_serial3_hw_init(void) 255 { 256 at91_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */ 257 at91_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */ 258 259 /* Enable clock */ 260 at91_periph_clk_enable(ATMEL_ID_USART3); 261 } 262 263 int board_early_init_f(void) 264 { 265 at91_periph_clk_enable(ATMEL_ID_PIOA); 266 at91_periph_clk_enable(ATMEL_ID_PIOB); 267 at91_periph_clk_enable(ATMEL_ID_PIOC); 268 at91_periph_clk_enable(ATMEL_ID_PIOD); 269 at91_periph_clk_enable(ATMEL_ID_PIOE); 270 271 sama5d4_xplained_serial3_hw_init(); 272 273 return 0; 274 } 275 276 int board_init(void) 277 { 278 /* adress of boot parameters */ 279 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 280 281 #ifdef CONFIG_ATMEL_SPI 282 sama5d4_xplained_spi0_hw_init(); 283 #endif 284 #ifdef CONFIG_NAND_ATMEL 285 sama5d4_xplained_nand_hw_init(); 286 #endif 287 #ifdef CONFIG_GENERIC_ATMEL_MCI 288 sama5d4_xplained_mci1_hw_init(); 289 #endif 290 #ifdef CONFIG_MACB 291 sama5d4_xplained_macb0_hw_init(); 292 #endif 293 #ifdef CONFIG_LCD 294 sama5d4_xplained_lcd_hw_init(); 295 #endif 296 #ifdef CONFIG_CMD_USB 297 sama5d4_xplained_usb_hw_init(); 298 #endif 299 300 return 0; 301 } 302 303 int dram_init(void) 304 { 305 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 306 CONFIG_SYS_SDRAM_SIZE); 307 return 0; 308 } 309 310 int board_eth_init(bd_t *bis) 311 { 312 int rc = 0; 313 314 #ifdef CONFIG_MACB 315 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00); 316 #endif 317 318 return rc; 319 } 320