1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2014 Atmel 4 * Bo Shen <voice.shen@atmel.com> 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <asm/arch/at91_common.h> 10 #include <asm/arch/at91_rstc.h> 11 #include <asm/arch/atmel_mpddrc.h> 12 #include <asm/arch/gpio.h> 13 #include <asm/arch/clk.h> 14 #include <asm/arch/sama5d3_smc.h> 15 #include <asm/arch/sama5d4.h> 16 #include <debug_uart.h> 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 #ifdef CONFIG_NAND_ATMEL 21 static void sama5d4_xplained_nand_hw_init(void) 22 { 23 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 24 25 at91_periph_clk_enable(ATMEL_ID_SMC); 26 27 /* Configure SMC CS3 for NAND */ 28 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | 29 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1), 30 &smc->cs[3].setup); 31 writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) | 32 AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3), 33 &smc->cs[3].pulse); 34 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), 35 &smc->cs[3].cycle); 36 writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) | 37 AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) | 38 AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3)| 39 AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); 40 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 41 AT91_SMC_MODE_EXNW_DISABLE | 42 AT91_SMC_MODE_DBW_8 | 43 AT91_SMC_MODE_TDF_CYCLE(3), 44 &smc->cs[3].mode); 45 46 at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */ 47 at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */ 48 at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */ 49 at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */ 50 at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */ 51 at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */ 52 at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */ 53 at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */ 54 at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */ 55 at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */ 56 at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */ 57 at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */ 58 at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */ 59 at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */ 60 } 61 #endif 62 63 #ifdef CONFIG_CMD_USB 64 static void sama5d4_xplained_usb_hw_init(void) 65 { 66 at91_set_pio_output(AT91_PIO_PORTE, 11, 1); 67 at91_set_pio_output(AT91_PIO_PORTE, 14, 1); 68 } 69 #endif 70 71 #ifdef CONFIG_BOARD_LATE_INIT 72 int board_late_init(void) 73 { 74 #ifdef CONFIG_DM_VIDEO 75 at91_video_show_board_info(); 76 #endif 77 return 0; 78 } 79 #endif 80 81 #ifdef CONFIG_DEBUG_UART_BOARD_INIT 82 static void sama5d4_xplained_serial3_hw_init(void) 83 { 84 at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */ 85 at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */ 86 87 /* Enable clock */ 88 at91_periph_clk_enable(ATMEL_ID_USART3); 89 } 90 91 void board_debug_uart_init(void) 92 { 93 sama5d4_xplained_serial3_hw_init(); 94 } 95 #endif 96 97 #ifdef CONFIG_BOARD_EARLY_INIT_F 98 int board_early_init_f(void) 99 { 100 #ifdef CONFIG_DEBUG_UART 101 debug_uart_init(); 102 #endif 103 return 0; 104 } 105 #endif 106 107 #define AT24MAC_MAC_OFFSET 0x9a 108 109 #ifdef CONFIG_MISC_INIT_R 110 int misc_init_r(void) 111 { 112 #ifdef CONFIG_I2C_EEPROM 113 at91_set_ethaddr(AT24MAC_MAC_OFFSET); 114 #endif 115 return 0; 116 } 117 #endif 118 119 int board_init(void) 120 { 121 /* adress of boot parameters */ 122 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 123 124 #ifdef CONFIG_NAND_ATMEL 125 sama5d4_xplained_nand_hw_init(); 126 #endif 127 #ifdef CONFIG_CMD_USB 128 sama5d4_xplained_usb_hw_init(); 129 #endif 130 131 return 0; 132 } 133 134 int dram_init(void) 135 { 136 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 137 CONFIG_SYS_SDRAM_SIZE); 138 return 0; 139 } 140 141 /* SPL */ 142 #ifdef CONFIG_SPL_BUILD 143 void spl_board_init(void) 144 { 145 #if CONFIG_NAND_BOOT 146 sama5d4_xplained_nand_hw_init(); 147 #endif 148 } 149 150 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) 151 { 152 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); 153 154 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | 155 ATMEL_MPDDRC_CR_NR_ROW_14 | 156 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | 157 ATMEL_MPDDRC_CR_NB_8BANKS | 158 ATMEL_MPDDRC_CR_NDQS_DISABLED | 159 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | 160 ATMEL_MPDDRC_CR_UNAL_SUPPORTED); 161 162 ddr2->rtr = 0x2b0; 163 164 ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | 165 3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | 166 3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | 167 10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | 168 3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | 169 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | 170 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | 171 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); 172 173 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | 174 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | 175 25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | 176 23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); 177 178 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | 179 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | 180 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | 181 2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | 182 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); 183 } 184 185 void mem_init(void) 186 { 187 struct atmel_mpddrc_config ddr2; 188 189 ddr2_conf(&ddr2); 190 191 /* Enable MPDDR clock */ 192 at91_periph_clk_enable(ATMEL_ID_MPDDRC); 193 at91_system_clk_enable(AT91_PMC_DDR); 194 195 /* DDRAM2 Controller initialize */ 196 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); 197 } 198 199 void at91_pmc_init(void) 200 { 201 u32 tmp; 202 203 tmp = AT91_PMC_PLLAR_29 | 204 AT91_PMC_PLLXR_PLLCOUNT(0x3f) | 205 AT91_PMC_PLLXR_MUL(87) | 206 AT91_PMC_PLLXR_DIV(1); 207 at91_plla_init(tmp); 208 209 at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x0)); 210 211 tmp = AT91_PMC_MCKR_H32MXDIV | 212 AT91_PMC_MCKR_PLLADIV_2 | 213 AT91_PMC_MCKR_MDIV_3 | 214 AT91_PMC_MCKR_CSS_PLLA; 215 at91_mck_init(tmp); 216 } 217 #endif 218