1 /* 2 * Copyright (C) 2014 Atmel 3 * Bo Shen <voice.shen@atmel.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <asm/arch/at91_common.h> 11 #include <asm/arch/at91_rstc.h> 12 #include <asm/arch/atmel_mpddrc.h> 13 #include <asm/arch/gpio.h> 14 #include <asm/arch/clk.h> 15 #include <asm/arch/sama5d3_smc.h> 16 #include <asm/arch/sama5d4.h> 17 #include <atmel_hlcdc.h> 18 #include <debug_uart.h> 19 #include <lcd.h> 20 #include <nand.h> 21 #include <version.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #ifdef CONFIG_NAND_ATMEL 26 static void sama5d4_xplained_nand_hw_init(void) 27 { 28 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 29 30 at91_periph_clk_enable(ATMEL_ID_SMC); 31 32 /* Configure SMC CS3 for NAND */ 33 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | 34 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1), 35 &smc->cs[3].setup); 36 writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) | 37 AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3), 38 &smc->cs[3].pulse); 39 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), 40 &smc->cs[3].cycle); 41 writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) | 42 AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) | 43 AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3)| 44 AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); 45 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 46 AT91_SMC_MODE_EXNW_DISABLE | 47 AT91_SMC_MODE_DBW_8 | 48 AT91_SMC_MODE_TDF_CYCLE(3), 49 &smc->cs[3].mode); 50 51 at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */ 52 at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */ 53 at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */ 54 at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */ 55 at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */ 56 at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */ 57 at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */ 58 at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */ 59 at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */ 60 at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */ 61 at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */ 62 at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */ 63 at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */ 64 at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */ 65 } 66 #endif 67 68 #ifdef CONFIG_CMD_USB 69 static void sama5d4_xplained_usb_hw_init(void) 70 { 71 at91_set_pio_output(AT91_PIO_PORTE, 11, 1); 72 at91_set_pio_output(AT91_PIO_PORTE, 14, 1); 73 } 74 #endif 75 76 #ifdef CONFIG_LCD 77 vidinfo_t panel_info = { 78 .vl_col = 480, 79 .vl_row = 272, 80 .vl_clk = 9000000, 81 .vl_bpix = LCD_BPP, 82 .vl_tft = 1, 83 .vl_hsync_len = 41, 84 .vl_left_margin = 2, 85 .vl_right_margin = 2, 86 .vl_vsync_len = 11, 87 .vl_upper_margin = 2, 88 .vl_lower_margin = 2, 89 .mmio = ATMEL_BASE_LCDC, 90 }; 91 92 /* No power up/down pin for the LCD pannel */ 93 void lcd_enable(void) { /* Empty! */ } 94 void lcd_disable(void) { /* Empty! */ } 95 96 unsigned int has_lcdc(void) 97 { 98 return 1; 99 } 100 101 static void sama5d4_xplained_lcd_hw_init(void) 102 { 103 at91_pio3_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */ 104 at91_pio3_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */ 105 at91_pio3_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */ 106 at91_pio3_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */ 107 at91_pio3_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */ 108 at91_pio3_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */ 109 110 at91_pio3_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */ 111 at91_pio3_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */ 112 at91_pio3_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */ 113 at91_pio3_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */ 114 at91_pio3_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */ 115 at91_pio3_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */ 116 at91_pio3_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */ 117 at91_pio3_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */ 118 119 at91_pio3_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD9 */ 120 at91_pio3_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD8 */ 121 at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */ 122 at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */ 123 at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */ 124 at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */ 125 at91_pio3_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */ 126 at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */ 127 128 at91_pio3_set_a_periph(AT91_PIO_PORTA, 16, 0); /* LCDD16 */ 129 at91_pio3_set_a_periph(AT91_PIO_PORTA, 17, 0); /* LCDD17 */ 130 at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */ 131 at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */ 132 at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */ 133 at91_pio3_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */ 134 at91_pio3_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */ 135 at91_pio3_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */ 136 137 /* Enable clock */ 138 at91_periph_clk_enable(ATMEL_ID_LCDC); 139 } 140 141 #ifdef CONFIG_LCD_INFO 142 void lcd_show_board_info(void) 143 { 144 ulong dram_size, nand_size; 145 int i; 146 char temp[32]; 147 148 lcd_printf("%s\n", U_BOOT_VERSION); 149 lcd_printf("2014 ATMEL Corp\n"); 150 lcd_printf("%s CPU at %s MHz\n", get_cpu_name(), 151 strmhz(temp, get_cpu_clk_rate())); 152 153 dram_size = 0; 154 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 155 dram_size += gd->bd->bi_dram[i].size; 156 157 nand_size = 0; 158 #ifdef CONFIG_NAND_ATMEL 159 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 160 nand_size += get_nand_dev_by_index(i)->size; 161 #endif 162 lcd_printf("%ld MB SDRAM, %ld MB NAND\n", 163 dram_size >> 20, nand_size >> 20); 164 } 165 #endif /* CONFIG_LCD_INFO */ 166 167 #endif /* CONFIG_LCD */ 168 169 #ifdef CONFIG_DEBUG_UART_BOARD_INIT 170 static void sama5d4_xplained_serial3_hw_init(void) 171 { 172 at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */ 173 at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */ 174 175 /* Enable clock */ 176 at91_periph_clk_enable(ATMEL_ID_USART3); 177 } 178 179 void board_debug_uart_init(void) 180 { 181 sama5d4_xplained_serial3_hw_init(); 182 } 183 #endif 184 185 #ifdef CONFIG_BOARD_EARLY_INIT_F 186 int board_early_init_f(void) 187 { 188 #ifdef CONFIG_DEBUG_UART 189 debug_uart_init(); 190 #endif 191 return 0; 192 } 193 #endif 194 195 #define AT24MAC_MAC_OFFSET 0x9a 196 197 #ifdef CONFIG_MISC_INIT_R 198 int misc_init_r(void) 199 { 200 #ifdef CONFIG_I2C_EEPROM 201 at91_set_ethaddr(AT24MAC_MAC_OFFSET); 202 #endif 203 return 0; 204 } 205 #endif 206 207 int board_init(void) 208 { 209 /* adress of boot parameters */ 210 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 211 212 #ifdef CONFIG_NAND_ATMEL 213 sama5d4_xplained_nand_hw_init(); 214 #endif 215 #ifdef CONFIG_LCD 216 sama5d4_xplained_lcd_hw_init(); 217 #endif 218 #ifdef CONFIG_CMD_USB 219 sama5d4_xplained_usb_hw_init(); 220 #endif 221 222 return 0; 223 } 224 225 int dram_init(void) 226 { 227 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 228 CONFIG_SYS_SDRAM_SIZE); 229 return 0; 230 } 231 232 /* SPL */ 233 #ifdef CONFIG_SPL_BUILD 234 void spl_board_init(void) 235 { 236 #if CONFIG_SYS_USE_NANDFLASH 237 sama5d4_xplained_nand_hw_init(); 238 #endif 239 } 240 241 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) 242 { 243 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); 244 245 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | 246 ATMEL_MPDDRC_CR_NR_ROW_14 | 247 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | 248 ATMEL_MPDDRC_CR_NB_8BANKS | 249 ATMEL_MPDDRC_CR_NDQS_DISABLED | 250 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | 251 ATMEL_MPDDRC_CR_UNAL_SUPPORTED); 252 253 ddr2->rtr = 0x2b0; 254 255 ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | 256 3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | 257 3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | 258 10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | 259 3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | 260 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | 261 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | 262 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); 263 264 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | 265 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | 266 25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | 267 23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); 268 269 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | 270 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | 271 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | 272 2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | 273 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); 274 } 275 276 void mem_init(void) 277 { 278 struct atmel_mpddrc_config ddr2; 279 280 ddr2_conf(&ddr2); 281 282 /* Enable MPDDR clock */ 283 at91_periph_clk_enable(ATMEL_ID_MPDDRC); 284 at91_system_clk_enable(AT91_PMC_DDR); 285 286 /* DDRAM2 Controller initialize */ 287 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); 288 } 289 290 void at91_pmc_init(void) 291 { 292 u32 tmp; 293 294 tmp = AT91_PMC_PLLAR_29 | 295 AT91_PMC_PLLXR_PLLCOUNT(0x3f) | 296 AT91_PMC_PLLXR_MUL(87) | 297 AT91_PMC_PLLXR_DIV(1); 298 at91_plla_init(tmp); 299 300 at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x0)); 301 302 tmp = AT91_PMC_MCKR_H32MXDIV | 303 AT91_PMC_MCKR_PLLADIV_2 | 304 AT91_PMC_MCKR_MDIV_3 | 305 AT91_PMC_MCKR_CSS_PLLA; 306 at91_mck_init(tmp); 307 } 308 #endif 309