1 /* 2 * Copyright (C) 2014 Atmel 3 * Bo Shen <voice.shen@atmel.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <asm/arch/at91_common.h> 11 #include <asm/arch/at91_pmc.h> 12 #include <asm/arch/at91_rstc.h> 13 #include <asm/arch/atmel_mpddrc.h> 14 #include <asm/arch/atmel_usba_udc.h> 15 #include <asm/arch/gpio.h> 16 #include <asm/arch/clk.h> 17 #include <asm/arch/sama5d3_smc.h> 18 #include <asm/arch/sama5d4.h> 19 #include <atmel_hlcdc.h> 20 #include <atmel_mci.h> 21 #include <lcd.h> 22 #include <mmc.h> 23 #include <net.h> 24 #include <netdev.h> 25 #include <nand.h> 26 #include <spi.h> 27 #include <version.h> 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 #ifdef CONFIG_ATMEL_SPI 32 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 33 { 34 return bus == 0 && cs == 0; 35 } 36 37 void spi_cs_activate(struct spi_slave *slave) 38 { 39 at91_set_pio_output(AT91_PIO_PORTC, 3, 0); 40 } 41 42 void spi_cs_deactivate(struct spi_slave *slave) 43 { 44 at91_set_pio_output(AT91_PIO_PORTC, 3, 1); 45 } 46 47 static void sama5d4_xplained_spi0_hw_init(void) 48 { 49 at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */ 50 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */ 51 at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */ 52 53 at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */ 54 55 /* Enable clock */ 56 at91_periph_clk_enable(ATMEL_ID_SPI0); 57 } 58 #endif /* CONFIG_ATMEL_SPI */ 59 60 #ifdef CONFIG_NAND_ATMEL 61 static void sama5d4_xplained_nand_hw_init(void) 62 { 63 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 64 65 at91_periph_clk_enable(ATMEL_ID_SMC); 66 67 /* Configure SMC CS3 for NAND */ 68 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | 69 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1), 70 &smc->cs[3].setup); 71 writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) | 72 AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3), 73 &smc->cs[3].pulse); 74 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), 75 &smc->cs[3].cycle); 76 writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) | 77 AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) | 78 AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3)| 79 AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); 80 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 81 AT91_SMC_MODE_EXNW_DISABLE | 82 AT91_SMC_MODE_DBW_8 | 83 AT91_SMC_MODE_TDF_CYCLE(3), 84 &smc->cs[3].mode); 85 86 at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */ 87 at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */ 88 at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */ 89 at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */ 90 at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */ 91 at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */ 92 at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */ 93 at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */ 94 at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */ 95 at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */ 96 at91_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */ 97 at91_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */ 98 at91_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */ 99 at91_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */ 100 } 101 #endif 102 103 #ifdef CONFIG_CMD_USB 104 static void sama5d4_xplained_usb_hw_init(void) 105 { 106 at91_set_pio_output(AT91_PIO_PORTE, 11, 1); 107 at91_set_pio_output(AT91_PIO_PORTE, 14, 1); 108 } 109 #endif 110 111 #ifdef CONFIG_LCD 112 vidinfo_t panel_info = { 113 .vl_col = 480, 114 .vl_row = 272, 115 .vl_clk = 9000000, 116 .vl_bpix = LCD_BPP, 117 .vl_tft = 1, 118 .vl_hsync_len = 41, 119 .vl_left_margin = 2, 120 .vl_right_margin = 2, 121 .vl_vsync_len = 11, 122 .vl_upper_margin = 2, 123 .vl_lower_margin = 2, 124 .mmio = ATMEL_BASE_LCDC, 125 }; 126 127 /* No power up/down pin for the LCD pannel */ 128 void lcd_enable(void) { /* Empty! */ } 129 void lcd_disable(void) { /* Empty! */ } 130 131 unsigned int has_lcdc(void) 132 { 133 return 1; 134 } 135 136 static void sama5d4_xplained_lcd_hw_init(void) 137 { 138 at91_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */ 139 at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */ 140 at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */ 141 at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */ 142 at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */ 143 at91_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */ 144 145 at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */ 146 at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */ 147 at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */ 148 at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */ 149 at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */ 150 at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */ 151 at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */ 152 at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */ 153 154 at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD9 */ 155 at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD8 */ 156 at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */ 157 at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */ 158 at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */ 159 at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */ 160 at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */ 161 at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */ 162 163 at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* LCDD16 */ 164 at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* LCDD17 */ 165 at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */ 166 at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */ 167 at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */ 168 at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */ 169 at91_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */ 170 at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */ 171 172 /* Enable clock */ 173 at91_periph_clk_enable(ATMEL_ID_LCDC); 174 } 175 176 #ifdef CONFIG_LCD_INFO 177 void lcd_show_board_info(void) 178 { 179 ulong dram_size, nand_size; 180 int i; 181 char temp[32]; 182 183 lcd_printf("%s\n", U_BOOT_VERSION); 184 lcd_printf("2014 ATMEL Corp\n"); 185 lcd_printf("%s CPU at %s MHz\n", get_cpu_name(), 186 strmhz(temp, get_cpu_clk_rate())); 187 188 dram_size = 0; 189 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 190 dram_size += gd->bd->bi_dram[i].size; 191 192 nand_size = 0; 193 #ifdef CONFIG_NAND_ATMEL 194 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 195 nand_size += nand_info[i].size; 196 #endif 197 lcd_printf("%ld MB SDRAM, %ld MB NAND\n", 198 dram_size >> 20, nand_size >> 20); 199 } 200 #endif /* CONFIG_LCD_INFO */ 201 202 #endif /* CONFIG_LCD */ 203 204 #ifdef CONFIG_GENERIC_ATMEL_MCI 205 void sama5d4_xplained_mci1_hw_init(void) 206 { 207 at91_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */ 208 at91_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */ 209 at91_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */ 210 at91_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */ 211 at91_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */ 212 at91_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */ 213 214 /* 215 * As the mci io internal pull down is too strong, so if the io needs 216 * external pull up, the pull up resistor will be very small, if so 217 * the power consumption will increase, so disable the interanl pull 218 * down to save the power. 219 */ 220 at91_set_pio_pulldown(AT91_PIO_PORTE, 18, 0); 221 at91_set_pio_pulldown(AT91_PIO_PORTE, 19, 0); 222 at91_set_pio_pulldown(AT91_PIO_PORTE, 20, 0); 223 at91_set_pio_pulldown(AT91_PIO_PORTE, 21, 0); 224 at91_set_pio_pulldown(AT91_PIO_PORTE, 22, 0); 225 at91_set_pio_pulldown(AT91_PIO_PORTE, 23, 0); 226 227 /* Enable clock */ 228 at91_periph_clk_enable(ATMEL_ID_MCI1); 229 } 230 231 int board_mmc_init(bd_t *bis) 232 { 233 /* Enable the power supply */ 234 at91_set_pio_output(AT91_PIO_PORTE, 4, 0); 235 236 return atmel_mci_init((void *)ATMEL_BASE_MCI1); 237 } 238 #endif /* CONFIG_GENERIC_ATMEL_MCI */ 239 240 #ifdef CONFIG_MACB 241 void sama5d4_xplained_macb0_hw_init(void) 242 { 243 at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */ 244 at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */ 245 at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */ 246 at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */ 247 at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */ 248 at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */ 249 at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */ 250 at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */ 251 at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */ 252 at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */ 253 254 /* Enable clock */ 255 at91_periph_clk_enable(ATMEL_ID_GMAC0); 256 } 257 #endif 258 259 static void sama5d4_xplained_serial3_hw_init(void) 260 { 261 at91_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */ 262 at91_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */ 263 264 /* Enable clock */ 265 at91_periph_clk_enable(ATMEL_ID_USART3); 266 } 267 268 int board_early_init_f(void) 269 { 270 at91_periph_clk_enable(ATMEL_ID_PIOA); 271 at91_periph_clk_enable(ATMEL_ID_PIOB); 272 at91_periph_clk_enable(ATMEL_ID_PIOC); 273 at91_periph_clk_enable(ATMEL_ID_PIOD); 274 at91_periph_clk_enable(ATMEL_ID_PIOE); 275 276 sama5d4_xplained_serial3_hw_init(); 277 278 return 0; 279 } 280 281 int board_init(void) 282 { 283 /* adress of boot parameters */ 284 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 285 286 #ifdef CONFIG_ATMEL_SPI 287 sama5d4_xplained_spi0_hw_init(); 288 #endif 289 #ifdef CONFIG_NAND_ATMEL 290 sama5d4_xplained_nand_hw_init(); 291 #endif 292 #ifdef CONFIG_GENERIC_ATMEL_MCI 293 sama5d4_xplained_mci1_hw_init(); 294 #endif 295 #ifdef CONFIG_MACB 296 sama5d4_xplained_macb0_hw_init(); 297 #endif 298 #ifdef CONFIG_LCD 299 sama5d4_xplained_lcd_hw_init(); 300 #endif 301 #ifdef CONFIG_CMD_USB 302 sama5d4_xplained_usb_hw_init(); 303 #endif 304 #ifdef CONFIG_USB_GADGET_ATMEL_USBA 305 at91_udp_hw_init(); 306 #endif 307 308 return 0; 309 } 310 311 int dram_init(void) 312 { 313 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 314 CONFIG_SYS_SDRAM_SIZE); 315 return 0; 316 } 317 318 int board_eth_init(bd_t *bis) 319 { 320 int rc = 0; 321 322 #ifdef CONFIG_MACB 323 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00); 324 #endif 325 326 #ifdef CONFIG_USB_GADGET_ATMEL_USBA 327 usba_udc_probe(&pdata); 328 #ifdef CONFIG_USB_ETH_RNDIS 329 usb_eth_initialize(bis); 330 #endif 331 #endif 332 333 return rc; 334 } 335 336 /* SPL */ 337 #ifdef CONFIG_SPL_BUILD 338 void spl_board_init(void) 339 { 340 #ifdef CONFIG_SYS_USE_MMC 341 sama5d4_xplained_mci1_hw_init(); 342 #elif CONFIG_SYS_USE_NANDFLASH 343 sama5d4_xplained_nand_hw_init(); 344 #elif CONFIG_SYS_USE_SERIALFLASH 345 sama5d4_xplained_spi0_hw_init(); 346 #endif 347 } 348 349 static void ddr2_conf(struct atmel_mpddr *ddr2) 350 { 351 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); 352 353 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | 354 ATMEL_MPDDRC_CR_NR_ROW_14 | 355 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | 356 ATMEL_MPDDRC_CR_NB_8BANKS | 357 ATMEL_MPDDRC_CR_NDQS_DISABLED | 358 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | 359 ATMEL_MPDDRC_CR_UNAL_SUPPORTED); 360 361 ddr2->rtr = 0x2b0; 362 363 ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | 364 3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | 365 3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | 366 10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | 367 3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | 368 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | 369 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | 370 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); 371 372 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | 373 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | 374 25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | 375 23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); 376 377 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | 378 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | 379 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | 380 2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | 381 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); 382 } 383 384 void mem_init(void) 385 { 386 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 387 struct atmel_mpddr ddr2; 388 389 ddr2_conf(&ddr2); 390 391 /* enable MPDDR clock */ 392 at91_periph_clk_enable(ATMEL_ID_MPDDRC); 393 writel(AT91_PMC_DDR, &pmc->scer); 394 395 /* DDRAM2 Controller initialize */ 396 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); 397 } 398 399 void at91_pmc_init(void) 400 { 401 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 402 u32 tmp; 403 404 tmp = AT91_PMC_PLLAR_29 | 405 AT91_PMC_PLLXR_PLLCOUNT(0x3f) | 406 AT91_PMC_PLLXR_MUL(87) | 407 AT91_PMC_PLLXR_DIV(1); 408 at91_plla_init(tmp); 409 410 writel(0x0 << 8, &pmc->pllicpr); 411 412 tmp = AT91_PMC_MCKR_H32MXDIV | 413 AT91_PMC_MCKR_PLLADIV_2 | 414 AT91_PMC_MCKR_MDIV_3 | 415 AT91_PMC_MCKR_CSS_PLLA; 416 at91_mck_init(tmp); 417 } 418 #endif 419