1 /* 2 * Copyright (C) 2012 - 2013 Atmel Corporation 3 * Bo Shen <voice.shen@atmel.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <mmc.h> 10 #include <asm/io.h> 11 #include <asm/arch/sama5d3_smc.h> 12 #include <asm/arch/at91_common.h> 13 #include <asm/arch/at91_pmc.h> 14 #include <asm/arch/at91_rstc.h> 15 #include <asm/arch/gpio.h> 16 #include <asm/arch/clk.h> 17 #include <lcd.h> 18 #include <atmel_lcdc.h> 19 #include <atmel_mci.h> 20 #include <micrel.h> 21 #include <net.h> 22 #include <netdev.h> 23 #include <spl.h> 24 #include <asm/arch/atmel_mpddrc.h> 25 #include <asm/arch/at91_wdt.h> 26 27 #ifdef CONFIG_USB_GADGET_ATMEL_USBA 28 #include <asm/arch/atmel_usba_udc.h> 29 #endif 30 31 DECLARE_GLOBAL_DATA_PTR; 32 33 /* ------------------------------------------------------------------------- */ 34 /* 35 * Miscelaneous platform dependent initialisations 36 */ 37 38 #ifdef CONFIG_NAND_ATMEL 39 void sama5d3xek_nand_hw_init(void) 40 { 41 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 42 43 at91_periph_clk_enable(ATMEL_ID_SMC); 44 45 /* Configure SMC CS3 for NAND/SmartMedia */ 46 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) | 47 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1), 48 &smc->cs[3].setup); 49 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | 50 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5), 51 &smc->cs[3].pulse); 52 writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8), 53 &smc->cs[3].cycle); 54 writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) | 55 AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) | 56 AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3)| 57 AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); 58 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 59 AT91_SMC_MODE_EXNW_DISABLE | 60 #ifdef CONFIG_SYS_NAND_DBW_16 61 AT91_SMC_MODE_DBW_16 | 62 #else /* CONFIG_SYS_NAND_DBW_8 */ 63 AT91_SMC_MODE_DBW_8 | 64 #endif 65 AT91_SMC_MODE_TDF_CYCLE(3), 66 &smc->cs[3].mode); 67 } 68 #endif 69 70 #ifndef CONFIG_SYS_NO_FLASH 71 static void sama5d3xek_nor_hw_init(void) 72 { 73 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 74 75 at91_periph_clk_enable(ATMEL_ID_SMC); 76 77 /* Configure SMC CS0 for NOR flash */ 78 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | 79 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), 80 &smc->cs[0].setup); 81 writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(11) | 82 AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(11), 83 &smc->cs[0].pulse); 84 writel(AT91_SMC_CYCLE_NWE(11) | AT91_SMC_CYCLE_NRD(14), 85 &smc->cs[0].cycle); 86 writel(AT91_SMC_TIMINGS_TCLR(0) | AT91_SMC_TIMINGS_TADL(0) | 87 AT91_SMC_TIMINGS_TAR(0) | AT91_SMC_TIMINGS_TRR(0) | 88 AT91_SMC_TIMINGS_TWB(0) | AT91_SMC_TIMINGS_RBNSEL(0)| 89 AT91_SMC_TIMINGS_NFSEL(0), &smc->cs[0].timings); 90 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 91 AT91_SMC_MODE_EXNW_DISABLE | 92 AT91_SMC_MODE_DBW_16 | 93 AT91_SMC_MODE_TDF_CYCLE(1), 94 &smc->cs[0].mode); 95 96 /* Address pin (A1 ~ A23) configuration */ 97 at91_set_a_periph(AT91_PIO_PORTE, 1, 0); 98 at91_set_a_periph(AT91_PIO_PORTE, 2, 0); 99 at91_set_a_periph(AT91_PIO_PORTE, 3, 0); 100 at91_set_a_periph(AT91_PIO_PORTE, 4, 0); 101 at91_set_a_periph(AT91_PIO_PORTE, 5, 0); 102 at91_set_a_periph(AT91_PIO_PORTE, 6, 0); 103 at91_set_a_periph(AT91_PIO_PORTE, 7, 0); 104 at91_set_a_periph(AT91_PIO_PORTE, 8, 0); 105 at91_set_a_periph(AT91_PIO_PORTE, 9, 0); 106 at91_set_a_periph(AT91_PIO_PORTE, 10, 0); 107 at91_set_a_periph(AT91_PIO_PORTE, 11, 0); 108 at91_set_a_periph(AT91_PIO_PORTE, 12, 0); 109 at91_set_a_periph(AT91_PIO_PORTE, 13, 0); 110 at91_set_a_periph(AT91_PIO_PORTE, 14, 0); 111 at91_set_a_periph(AT91_PIO_PORTE, 15, 0); 112 at91_set_a_periph(AT91_PIO_PORTE, 16, 0); 113 at91_set_a_periph(AT91_PIO_PORTE, 17, 0); 114 at91_set_a_periph(AT91_PIO_PORTE, 18, 0); 115 at91_set_a_periph(AT91_PIO_PORTE, 19, 0); 116 at91_set_a_periph(AT91_PIO_PORTE, 20, 0); 117 at91_set_a_periph(AT91_PIO_PORTE, 21, 0); 118 at91_set_a_periph(AT91_PIO_PORTE, 22, 0); 119 at91_set_a_periph(AT91_PIO_PORTE, 23, 0); 120 /* CS0 pin configuration */ 121 at91_set_a_periph(AT91_PIO_PORTE, 26, 0); 122 } 123 #endif 124 125 #ifdef CONFIG_CMD_USB 126 static void sama5d3xek_usb_hw_init(void) 127 { 128 at91_set_pio_output(AT91_PIO_PORTD, 25, 0); 129 at91_set_pio_output(AT91_PIO_PORTD, 26, 0); 130 at91_set_pio_output(AT91_PIO_PORTD, 27, 0); 131 } 132 #endif 133 134 #ifdef CONFIG_GENERIC_ATMEL_MCI 135 static void sama5d3xek_mci_hw_init(void) 136 { 137 at91_mci_hw_init(); 138 139 at91_set_pio_output(AT91_PIO_PORTB, 10, 0); /* MCI0 Power */ 140 } 141 #endif 142 143 #ifdef CONFIG_LCD 144 vidinfo_t panel_info = { 145 .vl_col = 800, 146 .vl_row = 480, 147 .vl_clk = 24000000, 148 .vl_sync = ATMEL_LCDC_INVLINE_NORMAL | ATMEL_LCDC_INVFRAME_NORMAL, 149 .vl_bpix = LCD_BPP, 150 .vl_tft = 1, 151 .vl_hsync_len = 128, 152 .vl_left_margin = 64, 153 .vl_right_margin = 64, 154 .vl_vsync_len = 2, 155 .vl_upper_margin = 22, 156 .vl_lower_margin = 21, 157 .mmio = ATMEL_BASE_LCDC, 158 }; 159 160 void lcd_enable(void) 161 { 162 } 163 164 void lcd_disable(void) 165 { 166 } 167 168 static void sama5d3xek_lcd_hw_init(void) 169 { 170 gd->fb_base = CONFIG_SAMA5D3_LCD_BASE; 171 172 /* The higher 8 bit of LCD is board related */ 173 at91_set_c_periph(AT91_PIO_PORTC, 14, 0); /* LCDD16 */ 174 at91_set_c_periph(AT91_PIO_PORTC, 13, 0); /* LCDD17 */ 175 at91_set_c_periph(AT91_PIO_PORTC, 12, 0); /* LCDD18 */ 176 at91_set_c_periph(AT91_PIO_PORTC, 11, 0); /* LCDD19 */ 177 at91_set_c_periph(AT91_PIO_PORTC, 10, 0); /* LCDD20 */ 178 at91_set_c_periph(AT91_PIO_PORTC, 15, 0); /* LCDD21 */ 179 at91_set_c_periph(AT91_PIO_PORTE, 27, 0); /* LCDD22 */ 180 at91_set_c_periph(AT91_PIO_PORTE, 28, 0); /* LCDD23 */ 181 182 /* Configure lower 16 bit of LCD and enable clock */ 183 at91_lcd_hw_init(); 184 } 185 186 #ifdef CONFIG_LCD_INFO 187 #include <nand.h> 188 #include <version.h> 189 190 void lcd_show_board_info(void) 191 { 192 ulong dram_size; 193 uint64_t nand_size; 194 int i; 195 char temp[32]; 196 197 lcd_printf("%s\n", U_BOOT_VERSION); 198 lcd_printf("(C) 2013 ATMEL Corp\n"); 199 lcd_printf("at91@atmel.com\n"); 200 lcd_printf("%s CPU at %s MHz\n", get_cpu_name(), 201 strmhz(temp, get_cpu_clk_rate())); 202 203 dram_size = 0; 204 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 205 dram_size += gd->bd->bi_dram[i].size; 206 207 nand_size = 0; 208 #ifdef CONFIG_NAND_ATMEL 209 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 210 nand_size += nand_info[i].size; 211 #endif 212 lcd_printf("%ld MB SDRAM, %lld MB NAND\n", 213 dram_size >> 20, nand_size >> 20); 214 } 215 #endif /* CONFIG_LCD_INFO */ 216 #endif /* CONFIG_LCD */ 217 218 int board_early_init_f(void) 219 { 220 at91_periph_clk_enable(ATMEL_ID_PIOA); 221 at91_periph_clk_enable(ATMEL_ID_PIOB); 222 at91_periph_clk_enable(ATMEL_ID_PIOC); 223 at91_periph_clk_enable(ATMEL_ID_PIOD); 224 at91_periph_clk_enable(ATMEL_ID_PIOE); 225 226 at91_seriald_hw_init(); 227 228 return 0; 229 } 230 231 int board_init(void) 232 { 233 /* adress of boot parameters */ 234 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 235 236 #ifdef CONFIG_NAND_ATMEL 237 sama5d3xek_nand_hw_init(); 238 #endif 239 #ifndef CONFIG_SYS_NO_FLASH 240 sama5d3xek_nor_hw_init(); 241 #endif 242 #ifdef CONFIG_CMD_USB 243 sama5d3xek_usb_hw_init(); 244 #endif 245 #ifdef CONFIG_USB_GADGET_ATMEL_USBA 246 at91_udp_hw_init(); 247 #endif 248 #ifdef CONFIG_GENERIC_ATMEL_MCI 249 sama5d3xek_mci_hw_init(); 250 #endif 251 #ifdef CONFIG_ATMEL_SPI 252 at91_spi0_hw_init(1 << 0); 253 #endif 254 #ifdef CONFIG_MACB 255 if (has_emac()) 256 at91_macb_hw_init(); 257 if (has_gmac()) 258 at91_gmac_hw_init(); 259 #endif 260 #ifdef CONFIG_LCD 261 if (has_lcdc()) 262 sama5d3xek_lcd_hw_init(); 263 #endif 264 return 0; 265 } 266 267 int dram_init(void) 268 { 269 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 270 CONFIG_SYS_SDRAM_SIZE); 271 return 0; 272 } 273 274 int board_phy_config(struct phy_device *phydev) 275 { 276 /* rx data delay */ 277 ksz9021_phy_extended_write(phydev, 278 MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x2222); 279 /* tx data delay */ 280 ksz9021_phy_extended_write(phydev, 281 MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x2222); 282 /* rx/tx clock delay */ 283 ksz9021_phy_extended_write(phydev, 284 MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf2f4); 285 286 return 0; 287 } 288 289 int board_eth_init(bd_t *bis) 290 { 291 int rc = 0; 292 293 #ifdef CONFIG_MACB 294 if (has_emac()) 295 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); 296 if (has_gmac()) 297 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00); 298 #endif 299 #ifdef CONFIG_USB_GADGET_ATMEL_USBA 300 usba_udc_probe(&pdata); 301 #ifdef CONFIG_USB_ETH_RNDIS 302 usb_eth_initialize(bis); 303 #endif 304 #endif 305 306 return rc; 307 } 308 309 #ifdef CONFIG_GENERIC_ATMEL_MCI 310 int board_mmc_init(bd_t *bis) 311 { 312 int rc = 0; 313 314 rc = atmel_mci_init((void *)ATMEL_BASE_MCI0); 315 316 return rc; 317 } 318 #endif 319 320 /* SPI chip select control */ 321 #ifdef CONFIG_ATMEL_SPI 322 #include <spi.h> 323 324 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 325 { 326 return bus == 0 && cs < 4; 327 } 328 329 void spi_cs_activate(struct spi_slave *slave) 330 { 331 switch (slave->cs) { 332 case 0: 333 at91_set_pio_output(AT91_PIO_PORTD, 13, 0); 334 case 1: 335 at91_set_pio_output(AT91_PIO_PORTD, 14, 0); 336 case 2: 337 at91_set_pio_output(AT91_PIO_PORTD, 15, 0); 338 case 3: 339 at91_set_pio_output(AT91_PIO_PORTD, 16, 0); 340 default: 341 break; 342 } 343 } 344 345 void spi_cs_deactivate(struct spi_slave *slave) 346 { 347 switch (slave->cs) { 348 case 0: 349 at91_set_pio_output(AT91_PIO_PORTD, 13, 1); 350 case 1: 351 at91_set_pio_output(AT91_PIO_PORTD, 14, 1); 352 case 2: 353 at91_set_pio_output(AT91_PIO_PORTD, 15, 1); 354 case 3: 355 at91_set_pio_output(AT91_PIO_PORTD, 16, 1); 356 default: 357 break; 358 } 359 } 360 #endif /* CONFIG_ATMEL_SPI */ 361 362 /* SPL */ 363 #ifdef CONFIG_SPL_BUILD 364 void spl_board_init(void) 365 { 366 #ifdef CONFIG_SYS_USE_MMC 367 sama5d3xek_mci_hw_init(); 368 #elif CONFIG_SYS_USE_NANDFLASH 369 sama5d3xek_nand_hw_init(); 370 #elif CONFIG_SYS_USE_SERIALFLASH 371 at91_spi0_hw_init(1 << 0); 372 #endif 373 } 374 375 static void ddr2_conf(struct atmel_mpddr *ddr2) 376 { 377 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); 378 379 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | 380 ATMEL_MPDDRC_CR_NR_ROW_14 | 381 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | 382 ATMEL_MPDDRC_CR_ENRDM_ON | 383 ATMEL_MPDDRC_CR_NB_8BANKS | 384 ATMEL_MPDDRC_CR_NDQS_DISABLED | 385 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | 386 ATMEL_MPDDRC_CR_UNAL_SUPPORTED); 387 /* 388 * As the DDR2-SDRAm device requires a refresh time is 7.8125us 389 * when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks 390 */ 391 ddr2->rtr = 0x411; 392 393 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | 394 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | 395 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | 396 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | 397 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | 398 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | 399 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | 400 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); 401 402 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | 403 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | 404 28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | 405 26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); 406 407 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | 408 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | 409 2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | 410 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | 411 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); 412 } 413 414 void mem_init(void) 415 { 416 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 417 struct atmel_mpddr ddr2; 418 419 ddr2_conf(&ddr2); 420 421 /* enable MPDDR clock */ 422 at91_periph_clk_enable(ATMEL_ID_MPDDRC); 423 writel(0x4, &pmc->scer); 424 425 /* DDRAM2 Controller initialize */ 426 ddr2_init(ATMEL_BASE_DDRCS, &ddr2); 427 } 428 429 void at91_pmc_init(void) 430 { 431 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 432 u32 tmp; 433 434 tmp = AT91_PMC_PLLAR_29 | 435 AT91_PMC_PLLXR_PLLCOUNT(0x3f) | 436 AT91_PMC_PLLXR_MUL(43) | 437 AT91_PMC_PLLXR_DIV(1); 438 at91_plla_init(tmp); 439 440 writel(0x3 << 8, &pmc->pllicpr); 441 442 tmp = AT91_PMC_MCKR_MDIV_4 | 443 AT91_PMC_MCKR_CSS_PLLA; 444 at91_mck_init(tmp); 445 } 446 #endif 447