1 /* 2 * Copyright (C) 2012 - 2013 Atmel Corporation 3 * Bo Shen <voice.shen@atmel.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <asm/arch/sama5d3_smc.h> 11 #include <asm/arch/at91_common.h> 12 #include <asm/arch/at91_rstc.h> 13 #include <asm/arch/gpio.h> 14 #include <asm/arch/clk.h> 15 #include <debug_uart.h> 16 #include <linux/ctype.h> 17 #include <phy.h> 18 #include <micrel.h> 19 #include <spl.h> 20 #include <asm/arch/atmel_mpddrc.h> 21 #include <asm/arch/at91_wdt.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 /* ------------------------------------------------------------------------- */ 26 /* 27 * Miscelaneous platform dependent initialisations 28 */ 29 30 #ifdef CONFIG_NAND_ATMEL 31 void sama5d3xek_nand_hw_init(void) 32 { 33 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 34 35 at91_periph_clk_enable(ATMEL_ID_SMC); 36 37 /* Configure SMC CS3 for NAND/SmartMedia */ 38 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) | 39 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1), 40 &smc->cs[3].setup); 41 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | 42 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5), 43 &smc->cs[3].pulse); 44 writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8), 45 &smc->cs[3].cycle); 46 writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) | 47 AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) | 48 AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3)| 49 AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); 50 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 51 AT91_SMC_MODE_EXNW_DISABLE | 52 #ifdef CONFIG_SYS_NAND_DBW_16 53 AT91_SMC_MODE_DBW_16 | 54 #else /* CONFIG_SYS_NAND_DBW_8 */ 55 AT91_SMC_MODE_DBW_8 | 56 #endif 57 AT91_SMC_MODE_TDF_CYCLE(3), 58 &smc->cs[3].mode); 59 } 60 #endif 61 62 #ifdef CONFIG_MTD_NOR_FLASH 63 static void sama5d3xek_nor_hw_init(void) 64 { 65 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 66 67 at91_periph_clk_enable(ATMEL_ID_SMC); 68 69 /* Configure SMC CS0 for NOR flash */ 70 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | 71 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), 72 &smc->cs[0].setup); 73 writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(11) | 74 AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(11), 75 &smc->cs[0].pulse); 76 writel(AT91_SMC_CYCLE_NWE(11) | AT91_SMC_CYCLE_NRD(14), 77 &smc->cs[0].cycle); 78 writel(AT91_SMC_TIMINGS_TCLR(0) | AT91_SMC_TIMINGS_TADL(0) | 79 AT91_SMC_TIMINGS_TAR(0) | AT91_SMC_TIMINGS_TRR(0) | 80 AT91_SMC_TIMINGS_TWB(0) | AT91_SMC_TIMINGS_RBNSEL(0)| 81 AT91_SMC_TIMINGS_NFSEL(0), &smc->cs[0].timings); 82 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 83 AT91_SMC_MODE_EXNW_DISABLE | 84 AT91_SMC_MODE_DBW_16 | 85 AT91_SMC_MODE_TDF_CYCLE(1), 86 &smc->cs[0].mode); 87 88 /* Address pin (A1 ~ A23) configuration */ 89 at91_pio3_set_a_periph(AT91_PIO_PORTE, 1, 0); 90 at91_pio3_set_a_periph(AT91_PIO_PORTE, 2, 0); 91 at91_pio3_set_a_periph(AT91_PIO_PORTE, 3, 0); 92 at91_pio3_set_a_periph(AT91_PIO_PORTE, 4, 0); 93 at91_pio3_set_a_periph(AT91_PIO_PORTE, 5, 0); 94 at91_pio3_set_a_periph(AT91_PIO_PORTE, 6, 0); 95 at91_pio3_set_a_periph(AT91_PIO_PORTE, 7, 0); 96 at91_pio3_set_a_periph(AT91_PIO_PORTE, 8, 0); 97 at91_pio3_set_a_periph(AT91_PIO_PORTE, 9, 0); 98 at91_pio3_set_a_periph(AT91_PIO_PORTE, 10, 0); 99 at91_pio3_set_a_periph(AT91_PIO_PORTE, 11, 0); 100 at91_pio3_set_a_periph(AT91_PIO_PORTE, 12, 0); 101 at91_pio3_set_a_periph(AT91_PIO_PORTE, 13, 0); 102 at91_pio3_set_a_periph(AT91_PIO_PORTE, 14, 0); 103 at91_pio3_set_a_periph(AT91_PIO_PORTE, 15, 0); 104 at91_pio3_set_a_periph(AT91_PIO_PORTE, 16, 0); 105 at91_pio3_set_a_periph(AT91_PIO_PORTE, 17, 0); 106 at91_pio3_set_a_periph(AT91_PIO_PORTE, 18, 0); 107 at91_pio3_set_a_periph(AT91_PIO_PORTE, 19, 0); 108 at91_pio3_set_a_periph(AT91_PIO_PORTE, 20, 0); 109 at91_pio3_set_a_periph(AT91_PIO_PORTE, 21, 0); 110 at91_pio3_set_a_periph(AT91_PIO_PORTE, 22, 0); 111 at91_pio3_set_a_periph(AT91_PIO_PORTE, 23, 0); 112 /* CS0 pin configuration */ 113 at91_pio3_set_a_periph(AT91_PIO_PORTE, 26, 0); 114 } 115 #endif 116 117 #ifdef CONFIG_CMD_USB 118 static void sama5d3xek_usb_hw_init(void) 119 { 120 at91_set_pio_output(AT91_PIO_PORTD, 25, 0); 121 at91_set_pio_output(AT91_PIO_PORTD, 26, 0); 122 at91_set_pio_output(AT91_PIO_PORTD, 27, 0); 123 } 124 #endif 125 126 #ifdef CONFIG_GENERIC_ATMEL_MCI 127 static void sama5d3xek_mci_hw_init(void) 128 { 129 at91_set_pio_output(AT91_PIO_PORTB, 10, 0); /* MCI0 Power */ 130 } 131 #endif 132 133 #ifdef CONFIG_DEBUG_UART_BOARD_INIT 134 void board_debug_uart_init(void) 135 { 136 at91_seriald_hw_init(); 137 } 138 #endif 139 140 #ifdef CONFIG_BOARD_EARLY_INIT_F 141 int board_early_init_f(void) 142 { 143 #ifdef CONFIG_DEBUG_UART 144 debug_uart_init(); 145 #endif 146 return 0; 147 } 148 #endif 149 150 int board_init(void) 151 { 152 /* adress of boot parameters */ 153 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 154 155 #ifdef CONFIG_NAND_ATMEL 156 sama5d3xek_nand_hw_init(); 157 #endif 158 #ifdef CONFIG_MTD_NOR_FLASH 159 sama5d3xek_nor_hw_init(); 160 #endif 161 #ifdef CONFIG_CMD_USB 162 sama5d3xek_usb_hw_init(); 163 #endif 164 #ifdef CONFIG_GENERIC_ATMEL_MCI 165 sama5d3xek_mci_hw_init(); 166 #endif 167 return 0; 168 } 169 170 int dram_init(void) 171 { 172 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 173 CONFIG_SYS_SDRAM_SIZE); 174 return 0; 175 } 176 177 #ifdef CONFIG_BOARD_LATE_INIT 178 int board_late_init(void) 179 { 180 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 181 const int MAX_STR_LEN = 32; 182 char name[MAX_STR_LEN], *p; 183 int i; 184 185 strncpy(name, get_cpu_name(), MAX_STR_LEN); 186 for (i = 0, p = name; (*p) && (i < MAX_STR_LEN); p++, i++) 187 *p = tolower(*p); 188 189 strcat(name, "ek.dtb"); 190 env_set("dtb_name", name); 191 #endif 192 #ifdef CONFIG_DM_VIDEO 193 at91_video_show_board_info(); 194 #endif 195 return 0; 196 } 197 #endif 198 199 /* SPL */ 200 #ifdef CONFIG_SPL_BUILD 201 void spl_board_init(void) 202 { 203 #if CONFIG_NAND_BOOT 204 sama5d3xek_nand_hw_init(); 205 #endif 206 } 207 208 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) 209 { 210 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); 211 212 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | 213 ATMEL_MPDDRC_CR_NR_ROW_14 | 214 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | 215 ATMEL_MPDDRC_CR_ENRDM_ON | 216 ATMEL_MPDDRC_CR_NB_8BANKS | 217 ATMEL_MPDDRC_CR_NDQS_DISABLED | 218 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | 219 ATMEL_MPDDRC_CR_UNAL_SUPPORTED); 220 /* 221 * As the DDR2-SDRAm device requires a refresh time is 7.8125us 222 * when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks 223 */ 224 ddr2->rtr = 0x411; 225 226 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | 227 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | 228 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | 229 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | 230 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | 231 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | 232 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | 233 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); 234 235 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | 236 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | 237 28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | 238 26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); 239 240 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | 241 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | 242 2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | 243 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | 244 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); 245 } 246 247 void mem_init(void) 248 { 249 struct atmel_mpddrc_config ddr2; 250 251 ddr2_conf(&ddr2); 252 253 /* Enable MPDDR clock */ 254 at91_periph_clk_enable(ATMEL_ID_MPDDRC); 255 at91_system_clk_enable(AT91_PMC_DDR); 256 257 /* DDRAM2 Controller initialize */ 258 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); 259 } 260 261 void at91_pmc_init(void) 262 { 263 u32 tmp; 264 265 tmp = AT91_PMC_PLLAR_29 | 266 AT91_PMC_PLLXR_PLLCOUNT(0x3f) | 267 AT91_PMC_PLLXR_MUL(43) | 268 AT91_PMC_PLLXR_DIV(1); 269 at91_plla_init(tmp); 270 271 at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3)); 272 273 tmp = AT91_PMC_MCKR_MDIV_4 | 274 AT91_PMC_MCKR_CSS_PLLA; 275 at91_mck_init(tmp); 276 } 277 #endif 278