1 /* 2 * Copyright (C) 2012 - 2013 Atmel Corporation 3 * Bo Shen <voice.shen@atmel.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <mmc.h> 10 #include <asm/io.h> 11 #include <asm/arch/sama5d3_smc.h> 12 #include <asm/arch/at91_common.h> 13 #include <asm/arch/at91_rstc.h> 14 #include <asm/arch/gpio.h> 15 #include <asm/arch/clk.h> 16 #include <lcd.h> 17 #include <linux/ctype.h> 18 #include <atmel_hlcdc.h> 19 #include <atmel_mci.h> 20 #include <phy.h> 21 #include <micrel.h> 22 #include <net.h> 23 #include <netdev.h> 24 #include <spl.h> 25 #include <asm/arch/atmel_mpddrc.h> 26 #include <asm/arch/at91_wdt.h> 27 28 #ifdef CONFIG_USB_GADGET_ATMEL_USBA 29 #include <asm/arch/atmel_usba_udc.h> 30 #endif 31 32 DECLARE_GLOBAL_DATA_PTR; 33 34 /* ------------------------------------------------------------------------- */ 35 /* 36 * Miscelaneous platform dependent initialisations 37 */ 38 39 #ifdef CONFIG_NAND_ATMEL 40 void sama5d3xek_nand_hw_init(void) 41 { 42 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 43 44 at91_periph_clk_enable(ATMEL_ID_SMC); 45 46 /* Configure SMC CS3 for NAND/SmartMedia */ 47 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) | 48 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1), 49 &smc->cs[3].setup); 50 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | 51 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5), 52 &smc->cs[3].pulse); 53 writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8), 54 &smc->cs[3].cycle); 55 writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) | 56 AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) | 57 AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3)| 58 AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); 59 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 60 AT91_SMC_MODE_EXNW_DISABLE | 61 #ifdef CONFIG_SYS_NAND_DBW_16 62 AT91_SMC_MODE_DBW_16 | 63 #else /* CONFIG_SYS_NAND_DBW_8 */ 64 AT91_SMC_MODE_DBW_8 | 65 #endif 66 AT91_SMC_MODE_TDF_CYCLE(3), 67 &smc->cs[3].mode); 68 } 69 #endif 70 71 #ifndef CONFIG_SYS_NO_FLASH 72 static void sama5d3xek_nor_hw_init(void) 73 { 74 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 75 76 at91_periph_clk_enable(ATMEL_ID_SMC); 77 78 /* Configure SMC CS0 for NOR flash */ 79 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | 80 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), 81 &smc->cs[0].setup); 82 writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(11) | 83 AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(11), 84 &smc->cs[0].pulse); 85 writel(AT91_SMC_CYCLE_NWE(11) | AT91_SMC_CYCLE_NRD(14), 86 &smc->cs[0].cycle); 87 writel(AT91_SMC_TIMINGS_TCLR(0) | AT91_SMC_TIMINGS_TADL(0) | 88 AT91_SMC_TIMINGS_TAR(0) | AT91_SMC_TIMINGS_TRR(0) | 89 AT91_SMC_TIMINGS_TWB(0) | AT91_SMC_TIMINGS_RBNSEL(0)| 90 AT91_SMC_TIMINGS_NFSEL(0), &smc->cs[0].timings); 91 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 92 AT91_SMC_MODE_EXNW_DISABLE | 93 AT91_SMC_MODE_DBW_16 | 94 AT91_SMC_MODE_TDF_CYCLE(1), 95 &smc->cs[0].mode); 96 97 /* Address pin (A1 ~ A23) configuration */ 98 at91_set_a_periph(AT91_PIO_PORTE, 1, 0); 99 at91_set_a_periph(AT91_PIO_PORTE, 2, 0); 100 at91_set_a_periph(AT91_PIO_PORTE, 3, 0); 101 at91_set_a_periph(AT91_PIO_PORTE, 4, 0); 102 at91_set_a_periph(AT91_PIO_PORTE, 5, 0); 103 at91_set_a_periph(AT91_PIO_PORTE, 6, 0); 104 at91_set_a_periph(AT91_PIO_PORTE, 7, 0); 105 at91_set_a_periph(AT91_PIO_PORTE, 8, 0); 106 at91_set_a_periph(AT91_PIO_PORTE, 9, 0); 107 at91_set_a_periph(AT91_PIO_PORTE, 10, 0); 108 at91_set_a_periph(AT91_PIO_PORTE, 11, 0); 109 at91_set_a_periph(AT91_PIO_PORTE, 12, 0); 110 at91_set_a_periph(AT91_PIO_PORTE, 13, 0); 111 at91_set_a_periph(AT91_PIO_PORTE, 14, 0); 112 at91_set_a_periph(AT91_PIO_PORTE, 15, 0); 113 at91_set_a_periph(AT91_PIO_PORTE, 16, 0); 114 at91_set_a_periph(AT91_PIO_PORTE, 17, 0); 115 at91_set_a_periph(AT91_PIO_PORTE, 18, 0); 116 at91_set_a_periph(AT91_PIO_PORTE, 19, 0); 117 at91_set_a_periph(AT91_PIO_PORTE, 20, 0); 118 at91_set_a_periph(AT91_PIO_PORTE, 21, 0); 119 at91_set_a_periph(AT91_PIO_PORTE, 22, 0); 120 at91_set_a_periph(AT91_PIO_PORTE, 23, 0); 121 /* CS0 pin configuration */ 122 at91_set_a_periph(AT91_PIO_PORTE, 26, 0); 123 } 124 #endif 125 126 #ifdef CONFIG_CMD_USB 127 static void sama5d3xek_usb_hw_init(void) 128 { 129 at91_set_pio_output(AT91_PIO_PORTD, 25, 0); 130 at91_set_pio_output(AT91_PIO_PORTD, 26, 0); 131 at91_set_pio_output(AT91_PIO_PORTD, 27, 0); 132 } 133 #endif 134 135 #ifdef CONFIG_GENERIC_ATMEL_MCI 136 static void sama5d3xek_mci_hw_init(void) 137 { 138 at91_mci_hw_init(); 139 140 at91_set_pio_output(AT91_PIO_PORTB, 10, 0); /* MCI0 Power */ 141 } 142 #endif 143 144 #ifdef CONFIG_LCD 145 vidinfo_t panel_info = { 146 .vl_col = 800, 147 .vl_row = 480, 148 .vl_clk = 24000000, 149 .vl_bpix = LCD_BPP, 150 .vl_tft = 1, 151 .vl_hsync_len = 128, 152 .vl_left_margin = 64, 153 .vl_right_margin = 64, 154 .vl_vsync_len = 2, 155 .vl_upper_margin = 22, 156 .vl_lower_margin = 21, 157 .mmio = ATMEL_BASE_LCDC, 158 }; 159 160 void lcd_enable(void) 161 { 162 } 163 164 void lcd_disable(void) 165 { 166 } 167 168 static void sama5d3xek_lcd_hw_init(void) 169 { 170 gd->fb_base = CONFIG_SAMA5D3_LCD_BASE; 171 172 /* The higher 8 bit of LCD is board related */ 173 at91_set_c_periph(AT91_PIO_PORTC, 14, 0); /* LCDD16 */ 174 at91_set_c_periph(AT91_PIO_PORTC, 13, 0); /* LCDD17 */ 175 at91_set_c_periph(AT91_PIO_PORTC, 12, 0); /* LCDD18 */ 176 at91_set_c_periph(AT91_PIO_PORTC, 11, 0); /* LCDD19 */ 177 at91_set_c_periph(AT91_PIO_PORTC, 10, 0); /* LCDD20 */ 178 at91_set_c_periph(AT91_PIO_PORTC, 15, 0); /* LCDD21 */ 179 at91_set_c_periph(AT91_PIO_PORTE, 27, 0); /* LCDD22 */ 180 at91_set_c_periph(AT91_PIO_PORTE, 28, 0); /* LCDD23 */ 181 182 /* Configure lower 16 bit of LCD and enable clock */ 183 at91_lcd_hw_init(); 184 } 185 186 #ifdef CONFIG_LCD_INFO 187 #include <nand.h> 188 #include <version.h> 189 190 void lcd_show_board_info(void) 191 { 192 ulong dram_size; 193 uint64_t nand_size; 194 int i; 195 char temp[32]; 196 197 lcd_printf("%s\n", U_BOOT_VERSION); 198 lcd_printf("(C) 2013 ATMEL Corp\n"); 199 lcd_printf("at91@atmel.com\n"); 200 lcd_printf("%s CPU at %s MHz\n", get_cpu_name(), 201 strmhz(temp, get_cpu_clk_rate())); 202 203 dram_size = 0; 204 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 205 dram_size += gd->bd->bi_dram[i].size; 206 207 nand_size = 0; 208 #ifdef CONFIG_NAND_ATMEL 209 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 210 nand_size += nand_info[i]->size; 211 #endif 212 lcd_printf("%ld MB SDRAM, %lld MB NAND\n", 213 dram_size >> 20, nand_size >> 20); 214 } 215 #endif /* CONFIG_LCD_INFO */ 216 #endif /* CONFIG_LCD */ 217 218 int board_early_init_f(void) 219 { 220 at91_periph_clk_enable(ATMEL_ID_PIOA); 221 at91_periph_clk_enable(ATMEL_ID_PIOB); 222 at91_periph_clk_enable(ATMEL_ID_PIOC); 223 at91_periph_clk_enable(ATMEL_ID_PIOD); 224 at91_periph_clk_enable(ATMEL_ID_PIOE); 225 226 at91_seriald_hw_init(); 227 228 return 0; 229 } 230 231 int board_init(void) 232 { 233 /* adress of boot parameters */ 234 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 235 236 #ifdef CONFIG_NAND_ATMEL 237 sama5d3xek_nand_hw_init(); 238 #endif 239 #ifndef CONFIG_SYS_NO_FLASH 240 sama5d3xek_nor_hw_init(); 241 #endif 242 #ifdef CONFIG_CMD_USB 243 sama5d3xek_usb_hw_init(); 244 #endif 245 #ifdef CONFIG_USB_GADGET_ATMEL_USBA 246 at91_udp_hw_init(); 247 #endif 248 #ifdef CONFIG_GENERIC_ATMEL_MCI 249 sama5d3xek_mci_hw_init(); 250 #endif 251 #ifdef CONFIG_ATMEL_SPI 252 at91_spi0_hw_init(1 << 0); 253 #endif 254 #ifdef CONFIG_MACB 255 if (has_emac()) 256 at91_macb_hw_init(); 257 if (has_gmac()) 258 at91_gmac_hw_init(); 259 #endif 260 #ifdef CONFIG_LCD 261 if (has_lcdc()) 262 sama5d3xek_lcd_hw_init(); 263 #endif 264 return 0; 265 } 266 267 int dram_init(void) 268 { 269 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 270 CONFIG_SYS_SDRAM_SIZE); 271 return 0; 272 } 273 274 int board_phy_config(struct phy_device *phydev) 275 { 276 /* board specific timings for GMAC */ 277 if (has_gmac()) { 278 /* rx data delay */ 279 ksz9021_phy_extended_write(phydev, 280 MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 281 0x2222); 282 /* tx data delay */ 283 ksz9021_phy_extended_write(phydev, 284 MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 285 0x2222); 286 /* rx/tx clock delay */ 287 ksz9021_phy_extended_write(phydev, 288 MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 289 0xf2f4); 290 } 291 292 /* always run the PHY's config routine */ 293 if (phydev->drv->config) 294 return phydev->drv->config(phydev); 295 296 return 0; 297 } 298 299 int board_eth_init(bd_t *bis) 300 { 301 int rc = 0; 302 303 #ifdef CONFIG_MACB 304 if (has_emac()) 305 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); 306 if (has_gmac()) 307 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00); 308 #endif 309 #ifdef CONFIG_USB_GADGET_ATMEL_USBA 310 usba_udc_probe(&pdata); 311 #ifdef CONFIG_USB_ETH_RNDIS 312 usb_eth_initialize(bis); 313 #endif 314 #endif 315 316 return rc; 317 } 318 319 #ifdef CONFIG_GENERIC_ATMEL_MCI 320 int board_mmc_init(bd_t *bis) 321 { 322 int rc = 0; 323 324 rc = atmel_mci_init((void *)ATMEL_BASE_MCI0); 325 326 return rc; 327 } 328 #endif 329 330 /* SPI chip select control */ 331 #ifdef CONFIG_ATMEL_SPI 332 #include <spi.h> 333 334 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 335 { 336 return bus == 0 && cs < 4; 337 } 338 339 void spi_cs_activate(struct spi_slave *slave) 340 { 341 switch (slave->cs) { 342 case 0: 343 at91_set_pio_output(AT91_PIO_PORTD, 13, 0); 344 case 1: 345 at91_set_pio_output(AT91_PIO_PORTD, 14, 0); 346 case 2: 347 at91_set_pio_output(AT91_PIO_PORTD, 15, 0); 348 case 3: 349 at91_set_pio_output(AT91_PIO_PORTD, 16, 0); 350 default: 351 break; 352 } 353 } 354 355 void spi_cs_deactivate(struct spi_slave *slave) 356 { 357 switch (slave->cs) { 358 case 0: 359 at91_set_pio_output(AT91_PIO_PORTD, 13, 1); 360 case 1: 361 at91_set_pio_output(AT91_PIO_PORTD, 14, 1); 362 case 2: 363 at91_set_pio_output(AT91_PIO_PORTD, 15, 1); 364 case 3: 365 at91_set_pio_output(AT91_PIO_PORTD, 16, 1); 366 default: 367 break; 368 } 369 } 370 #endif /* CONFIG_ATMEL_SPI */ 371 372 #ifdef CONFIG_BOARD_LATE_INIT 373 int board_late_init(void) 374 { 375 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 376 const int MAX_STR_LEN = 32; 377 char name[MAX_STR_LEN], *p; 378 int i; 379 380 strncpy(name, get_cpu_name(), MAX_STR_LEN); 381 for (i = 0, p = name; (*p) && (i < MAX_STR_LEN); p++, i++) 382 *p = tolower(*p); 383 384 strcat(name, "ek.dtb"); 385 setenv("dtb_name", name); 386 #endif 387 return 0; 388 } 389 #endif 390 391 /* SPL */ 392 #ifdef CONFIG_SPL_BUILD 393 void spl_board_init(void) 394 { 395 #ifdef CONFIG_SYS_USE_MMC 396 sama5d3xek_mci_hw_init(); 397 #elif CONFIG_SYS_USE_NANDFLASH 398 sama5d3xek_nand_hw_init(); 399 #elif CONFIG_SYS_USE_SERIALFLASH 400 at91_spi0_hw_init(1 << 0); 401 #endif 402 } 403 404 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) 405 { 406 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); 407 408 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | 409 ATMEL_MPDDRC_CR_NR_ROW_14 | 410 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | 411 ATMEL_MPDDRC_CR_ENRDM_ON | 412 ATMEL_MPDDRC_CR_NB_8BANKS | 413 ATMEL_MPDDRC_CR_NDQS_DISABLED | 414 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | 415 ATMEL_MPDDRC_CR_UNAL_SUPPORTED); 416 /* 417 * As the DDR2-SDRAm device requires a refresh time is 7.8125us 418 * when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks 419 */ 420 ddr2->rtr = 0x411; 421 422 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | 423 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | 424 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | 425 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | 426 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | 427 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | 428 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | 429 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); 430 431 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | 432 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | 433 28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | 434 26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); 435 436 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | 437 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | 438 2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | 439 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | 440 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); 441 } 442 443 void mem_init(void) 444 { 445 struct atmel_mpddrc_config ddr2; 446 447 ddr2_conf(&ddr2); 448 449 /* Enable MPDDR clock */ 450 at91_periph_clk_enable(ATMEL_ID_MPDDRC); 451 at91_system_clk_enable(AT91_PMC_DDR); 452 453 /* DDRAM2 Controller initialize */ 454 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); 455 } 456 457 void at91_pmc_init(void) 458 { 459 u32 tmp; 460 461 tmp = AT91_PMC_PLLAR_29 | 462 AT91_PMC_PLLXR_PLLCOUNT(0x3f) | 463 AT91_PMC_PLLXR_MUL(43) | 464 AT91_PMC_PLLXR_DIV(1); 465 at91_plla_init(tmp); 466 467 at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3)); 468 469 tmp = AT91_PMC_MCKR_MDIV_4 | 470 AT91_PMC_MCKR_CSS_PLLA; 471 at91_mck_init(tmp); 472 } 473 #endif 474