1 /* 2 * Copyright (C) 2012 - 2013 Atmel Corporation 3 * Bo Shen <voice.shen@atmel.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <mmc.h> 10 #include <asm/io.h> 11 #include <asm/arch/sama5d3_smc.h> 12 #include <asm/arch/at91_common.h> 13 #include <asm/arch/at91_pmc.h> 14 #include <asm/arch/at91_rstc.h> 15 #include <asm/arch/gpio.h> 16 #include <asm/arch/clk.h> 17 #include <lcd.h> 18 #include <atmel_lcdc.h> 19 #include <atmel_mci.h> 20 #include <micrel.h> 21 #include <net.h> 22 #include <netdev.h> 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 /* ------------------------------------------------------------------------- */ 27 /* 28 * Miscelaneous platform dependent initialisations 29 */ 30 31 #ifdef CONFIG_NAND_ATMEL 32 void sama5d3xek_nand_hw_init(void) 33 { 34 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 35 36 at91_periph_clk_enable(ATMEL_ID_SMC); 37 38 /* Configure SMC CS3 for NAND/SmartMedia */ 39 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) | 40 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1), 41 &smc->cs[3].setup); 42 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | 43 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5), 44 &smc->cs[3].pulse); 45 writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8), 46 &smc->cs[3].cycle); 47 writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) | 48 AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) | 49 AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3)| 50 AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); 51 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 52 AT91_SMC_MODE_EXNW_DISABLE | 53 #ifdef CONFIG_SYS_NAND_DBW_16 54 AT91_SMC_MODE_DBW_16 | 55 #else /* CONFIG_SYS_NAND_DBW_8 */ 56 AT91_SMC_MODE_DBW_8 | 57 #endif 58 AT91_SMC_MODE_TDF_CYCLE(3), 59 &smc->cs[3].mode); 60 } 61 #endif 62 63 #ifdef CONFIG_CMD_USB 64 static void sama5d3xek_usb_hw_init(void) 65 { 66 at91_set_pio_output(AT91_PIO_PORTD, 25, 0); 67 at91_set_pio_output(AT91_PIO_PORTD, 26, 0); 68 at91_set_pio_output(AT91_PIO_PORTD, 27, 0); 69 } 70 #endif 71 72 #ifdef CONFIG_GENERIC_ATMEL_MCI 73 static void sama5d3xek_mci_hw_init(void) 74 { 75 at91_mci_hw_init(); 76 77 at91_set_pio_output(AT91_PIO_PORTB, 10, 0); /* MCI0 Power */ 78 } 79 #endif 80 81 #ifdef CONFIG_LCD 82 vidinfo_t panel_info = { 83 .vl_col = 800, 84 .vl_row = 480, 85 .vl_clk = 24000000, 86 .vl_sync = ATMEL_LCDC_INVLINE_NORMAL | ATMEL_LCDC_INVFRAME_NORMAL, 87 .vl_bpix = LCD_BPP, 88 .vl_tft = 1, 89 .vl_hsync_len = 128, 90 .vl_left_margin = 64, 91 .vl_right_margin = 64, 92 .vl_vsync_len = 2, 93 .vl_upper_margin = 22, 94 .vl_lower_margin = 21, 95 .mmio = ATMEL_BASE_LCDC, 96 }; 97 98 void lcd_enable(void) 99 { 100 } 101 102 void lcd_disable(void) 103 { 104 } 105 106 static void sama5d3xek_lcd_hw_init(void) 107 { 108 gd->fb_base = CONFIG_SAMA5D3_LCD_BASE; 109 110 /* The higher 8 bit of LCD is board related */ 111 at91_set_c_periph(AT91_PIO_PORTC, 14, 0); /* LCDD16 */ 112 at91_set_c_periph(AT91_PIO_PORTC, 13, 0); /* LCDD17 */ 113 at91_set_c_periph(AT91_PIO_PORTC, 12, 0); /* LCDD18 */ 114 at91_set_c_periph(AT91_PIO_PORTC, 11, 0); /* LCDD19 */ 115 at91_set_c_periph(AT91_PIO_PORTC, 10, 0); /* LCDD20 */ 116 at91_set_c_periph(AT91_PIO_PORTC, 15, 0); /* LCDD21 */ 117 at91_set_c_periph(AT91_PIO_PORTE, 27, 0); /* LCDD22 */ 118 at91_set_c_periph(AT91_PIO_PORTE, 28, 0); /* LCDD23 */ 119 120 /* Configure lower 16 bit of LCD and enable clock */ 121 at91_lcd_hw_init(); 122 } 123 124 #ifdef CONFIG_LCD_INFO 125 #include <nand.h> 126 #include <version.h> 127 128 void lcd_show_board_info(void) 129 { 130 ulong dram_size, nand_size; 131 int i; 132 char temp[32]; 133 134 lcd_printf("%s\n", U_BOOT_VERSION); 135 lcd_printf("(C) 2013 ATMEL Corp\n"); 136 lcd_printf("at91@atmel.com\n"); 137 lcd_printf("%s CPU at %s MHz\n", get_cpu_name(), 138 strmhz(temp, get_cpu_clk_rate())); 139 140 dram_size = 0; 141 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 142 dram_size += gd->bd->bi_dram[i].size; 143 144 nand_size = 0; 145 #ifdef CONFIG_NAND_ATMEL 146 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 147 nand_size += nand_info[i].size; 148 #endif 149 lcd_printf("%ld MB SDRAM, %ld MB NAND\n", 150 dram_size >> 20, nand_size >> 20); 151 } 152 #endif /* CONFIG_LCD_INFO */ 153 #endif /* CONFIG_LCD */ 154 155 int board_early_init_f(void) 156 { 157 at91_seriald_hw_init(); 158 159 return 0; 160 } 161 162 int board_init(void) 163 { 164 /* adress of boot parameters */ 165 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 166 167 #ifdef CONFIG_NAND_ATMEL 168 sama5d3xek_nand_hw_init(); 169 #endif 170 #ifdef CONFIG_CMD_USB 171 sama5d3xek_usb_hw_init(); 172 #endif 173 #ifdef CONFIG_GENERIC_ATMEL_MCI 174 sama5d3xek_mci_hw_init(); 175 #endif 176 #ifdef CONFIG_ATMEL_SPI 177 at91_spi0_hw_init(1 << 0); 178 #endif 179 #ifdef CONFIG_MACB 180 if (has_emac()) 181 at91_macb_hw_init(); 182 if (has_gmac()) 183 at91_gmac_hw_init(); 184 #endif 185 #ifdef CONFIG_LCD 186 if (has_lcdc()) 187 sama5d3xek_lcd_hw_init(); 188 #endif 189 return 0; 190 } 191 192 int dram_init(void) 193 { 194 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 195 CONFIG_SYS_SDRAM_SIZE); 196 return 0; 197 } 198 199 int board_phy_config(struct phy_device *phydev) 200 { 201 /* rx data delay */ 202 ksz9021_phy_extended_write(phydev, 203 MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x2222); 204 /* tx data delay */ 205 ksz9021_phy_extended_write(phydev, 206 MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x2222); 207 /* rx/tx clock delay */ 208 ksz9021_phy_extended_write(phydev, 209 MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf2f4); 210 211 return 0; 212 } 213 214 int board_eth_init(bd_t *bis) 215 { 216 int rc = 0; 217 218 #ifdef CONFIG_MACB 219 if (has_emac()) 220 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); 221 if (has_gmac()) 222 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00); 223 #endif 224 225 return rc; 226 } 227 228 #ifdef CONFIG_GENERIC_ATMEL_MCI 229 int board_mmc_init(bd_t *bis) 230 { 231 int rc = 0; 232 233 rc = atmel_mci_init((void *)ATMEL_BASE_MCI0); 234 235 return rc; 236 } 237 #endif 238 239 /* SPI chip select control */ 240 #ifdef CONFIG_ATMEL_SPI 241 #include <spi.h> 242 243 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 244 { 245 return bus == 0 && cs < 4; 246 } 247 248 void spi_cs_activate(struct spi_slave *slave) 249 { 250 switch (slave->cs) { 251 case 0: 252 at91_set_pio_output(AT91_PIO_PORTD, 13, 0); 253 case 1: 254 at91_set_pio_output(AT91_PIO_PORTD, 14, 0); 255 case 2: 256 at91_set_pio_output(AT91_PIO_PORTD, 15, 0); 257 case 3: 258 at91_set_pio_output(AT91_PIO_PORTD, 16, 0); 259 default: 260 break; 261 } 262 } 263 264 void spi_cs_deactivate(struct spi_slave *slave) 265 { 266 switch (slave->cs) { 267 case 0: 268 at91_set_pio_output(AT91_PIO_PORTD, 13, 1); 269 case 1: 270 at91_set_pio_output(AT91_PIO_PORTD, 14, 1); 271 case 2: 272 at91_set_pio_output(AT91_PIO_PORTD, 15, 1); 273 case 3: 274 at91_set_pio_output(AT91_PIO_PORTD, 16, 1); 275 default: 276 break; 277 } 278 } 279 #endif /* CONFIG_ATMEL_SPI */ 280