1 /* 2 * Copyright (C) 2012 - 2013 Atmel Corporation 3 * Bo Shen <voice.shen@atmel.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <mmc.h> 10 #include <asm/io.h> 11 #include <asm/arch/sama5d3_smc.h> 12 #include <asm/arch/at91_common.h> 13 #include <asm/arch/at91_pmc.h> 14 #include <asm/arch/at91_rstc.h> 15 #include <asm/arch/gpio.h> 16 #include <asm/arch/clk.h> 17 #include <lcd.h> 18 #include <linux/ctype.h> 19 #include <atmel_hlcdc.h> 20 #include <atmel_mci.h> 21 #include <phy.h> 22 #include <micrel.h> 23 #include <net.h> 24 #include <netdev.h> 25 #include <spl.h> 26 #include <asm/arch/atmel_mpddrc.h> 27 #include <asm/arch/at91_wdt.h> 28 29 #ifdef CONFIG_USB_GADGET_ATMEL_USBA 30 #include <asm/arch/atmel_usba_udc.h> 31 #endif 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 /* ------------------------------------------------------------------------- */ 36 /* 37 * Miscelaneous platform dependent initialisations 38 */ 39 40 #ifdef CONFIG_NAND_ATMEL 41 void sama5d3xek_nand_hw_init(void) 42 { 43 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 44 45 at91_periph_clk_enable(ATMEL_ID_SMC); 46 47 /* Configure SMC CS3 for NAND/SmartMedia */ 48 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) | 49 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1), 50 &smc->cs[3].setup); 51 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | 52 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5), 53 &smc->cs[3].pulse); 54 writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8), 55 &smc->cs[3].cycle); 56 writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) | 57 AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) | 58 AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3)| 59 AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); 60 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 61 AT91_SMC_MODE_EXNW_DISABLE | 62 #ifdef CONFIG_SYS_NAND_DBW_16 63 AT91_SMC_MODE_DBW_16 | 64 #else /* CONFIG_SYS_NAND_DBW_8 */ 65 AT91_SMC_MODE_DBW_8 | 66 #endif 67 AT91_SMC_MODE_TDF_CYCLE(3), 68 &smc->cs[3].mode); 69 } 70 #endif 71 72 #ifndef CONFIG_SYS_NO_FLASH 73 static void sama5d3xek_nor_hw_init(void) 74 { 75 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 76 77 at91_periph_clk_enable(ATMEL_ID_SMC); 78 79 /* Configure SMC CS0 for NOR flash */ 80 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | 81 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), 82 &smc->cs[0].setup); 83 writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(11) | 84 AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(11), 85 &smc->cs[0].pulse); 86 writel(AT91_SMC_CYCLE_NWE(11) | AT91_SMC_CYCLE_NRD(14), 87 &smc->cs[0].cycle); 88 writel(AT91_SMC_TIMINGS_TCLR(0) | AT91_SMC_TIMINGS_TADL(0) | 89 AT91_SMC_TIMINGS_TAR(0) | AT91_SMC_TIMINGS_TRR(0) | 90 AT91_SMC_TIMINGS_TWB(0) | AT91_SMC_TIMINGS_RBNSEL(0)| 91 AT91_SMC_TIMINGS_NFSEL(0), &smc->cs[0].timings); 92 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 93 AT91_SMC_MODE_EXNW_DISABLE | 94 AT91_SMC_MODE_DBW_16 | 95 AT91_SMC_MODE_TDF_CYCLE(1), 96 &smc->cs[0].mode); 97 98 /* Address pin (A1 ~ A23) configuration */ 99 at91_set_a_periph(AT91_PIO_PORTE, 1, 0); 100 at91_set_a_periph(AT91_PIO_PORTE, 2, 0); 101 at91_set_a_periph(AT91_PIO_PORTE, 3, 0); 102 at91_set_a_periph(AT91_PIO_PORTE, 4, 0); 103 at91_set_a_periph(AT91_PIO_PORTE, 5, 0); 104 at91_set_a_periph(AT91_PIO_PORTE, 6, 0); 105 at91_set_a_periph(AT91_PIO_PORTE, 7, 0); 106 at91_set_a_periph(AT91_PIO_PORTE, 8, 0); 107 at91_set_a_periph(AT91_PIO_PORTE, 9, 0); 108 at91_set_a_periph(AT91_PIO_PORTE, 10, 0); 109 at91_set_a_periph(AT91_PIO_PORTE, 11, 0); 110 at91_set_a_periph(AT91_PIO_PORTE, 12, 0); 111 at91_set_a_periph(AT91_PIO_PORTE, 13, 0); 112 at91_set_a_periph(AT91_PIO_PORTE, 14, 0); 113 at91_set_a_periph(AT91_PIO_PORTE, 15, 0); 114 at91_set_a_periph(AT91_PIO_PORTE, 16, 0); 115 at91_set_a_periph(AT91_PIO_PORTE, 17, 0); 116 at91_set_a_periph(AT91_PIO_PORTE, 18, 0); 117 at91_set_a_periph(AT91_PIO_PORTE, 19, 0); 118 at91_set_a_periph(AT91_PIO_PORTE, 20, 0); 119 at91_set_a_periph(AT91_PIO_PORTE, 21, 0); 120 at91_set_a_periph(AT91_PIO_PORTE, 22, 0); 121 at91_set_a_periph(AT91_PIO_PORTE, 23, 0); 122 /* CS0 pin configuration */ 123 at91_set_a_periph(AT91_PIO_PORTE, 26, 0); 124 } 125 #endif 126 127 #ifdef CONFIG_CMD_USB 128 static void sama5d3xek_usb_hw_init(void) 129 { 130 at91_set_pio_output(AT91_PIO_PORTD, 25, 0); 131 at91_set_pio_output(AT91_PIO_PORTD, 26, 0); 132 at91_set_pio_output(AT91_PIO_PORTD, 27, 0); 133 } 134 #endif 135 136 #ifdef CONFIG_GENERIC_ATMEL_MCI 137 static void sama5d3xek_mci_hw_init(void) 138 { 139 at91_mci_hw_init(); 140 141 at91_set_pio_output(AT91_PIO_PORTB, 10, 0); /* MCI0 Power */ 142 } 143 #endif 144 145 #ifdef CONFIG_LCD 146 vidinfo_t panel_info = { 147 .vl_col = 800, 148 .vl_row = 480, 149 .vl_clk = 24000000, 150 .vl_bpix = LCD_BPP, 151 .vl_tft = 1, 152 .vl_hsync_len = 128, 153 .vl_left_margin = 64, 154 .vl_right_margin = 64, 155 .vl_vsync_len = 2, 156 .vl_upper_margin = 22, 157 .vl_lower_margin = 21, 158 .mmio = ATMEL_BASE_LCDC, 159 }; 160 161 void lcd_enable(void) 162 { 163 } 164 165 void lcd_disable(void) 166 { 167 } 168 169 static void sama5d3xek_lcd_hw_init(void) 170 { 171 gd->fb_base = CONFIG_SAMA5D3_LCD_BASE; 172 173 /* The higher 8 bit of LCD is board related */ 174 at91_set_c_periph(AT91_PIO_PORTC, 14, 0); /* LCDD16 */ 175 at91_set_c_periph(AT91_PIO_PORTC, 13, 0); /* LCDD17 */ 176 at91_set_c_periph(AT91_PIO_PORTC, 12, 0); /* LCDD18 */ 177 at91_set_c_periph(AT91_PIO_PORTC, 11, 0); /* LCDD19 */ 178 at91_set_c_periph(AT91_PIO_PORTC, 10, 0); /* LCDD20 */ 179 at91_set_c_periph(AT91_PIO_PORTC, 15, 0); /* LCDD21 */ 180 at91_set_c_periph(AT91_PIO_PORTE, 27, 0); /* LCDD22 */ 181 at91_set_c_periph(AT91_PIO_PORTE, 28, 0); /* LCDD23 */ 182 183 /* Configure lower 16 bit of LCD and enable clock */ 184 at91_lcd_hw_init(); 185 } 186 187 #ifdef CONFIG_LCD_INFO 188 #include <nand.h> 189 #include <version.h> 190 191 void lcd_show_board_info(void) 192 { 193 ulong dram_size; 194 uint64_t nand_size; 195 int i; 196 char temp[32]; 197 198 lcd_printf("%s\n", U_BOOT_VERSION); 199 lcd_printf("(C) 2013 ATMEL Corp\n"); 200 lcd_printf("at91@atmel.com\n"); 201 lcd_printf("%s CPU at %s MHz\n", get_cpu_name(), 202 strmhz(temp, get_cpu_clk_rate())); 203 204 dram_size = 0; 205 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 206 dram_size += gd->bd->bi_dram[i].size; 207 208 nand_size = 0; 209 #ifdef CONFIG_NAND_ATMEL 210 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 211 nand_size += nand_info[i].size; 212 #endif 213 lcd_printf("%ld MB SDRAM, %lld MB NAND\n", 214 dram_size >> 20, nand_size >> 20); 215 } 216 #endif /* CONFIG_LCD_INFO */ 217 #endif /* CONFIG_LCD */ 218 219 int board_early_init_f(void) 220 { 221 at91_periph_clk_enable(ATMEL_ID_PIOA); 222 at91_periph_clk_enable(ATMEL_ID_PIOB); 223 at91_periph_clk_enable(ATMEL_ID_PIOC); 224 at91_periph_clk_enable(ATMEL_ID_PIOD); 225 at91_periph_clk_enable(ATMEL_ID_PIOE); 226 227 at91_seriald_hw_init(); 228 229 return 0; 230 } 231 232 int board_init(void) 233 { 234 /* adress of boot parameters */ 235 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 236 237 #ifdef CONFIG_NAND_ATMEL 238 sama5d3xek_nand_hw_init(); 239 #endif 240 #ifndef CONFIG_SYS_NO_FLASH 241 sama5d3xek_nor_hw_init(); 242 #endif 243 #ifdef CONFIG_CMD_USB 244 sama5d3xek_usb_hw_init(); 245 #endif 246 #ifdef CONFIG_USB_GADGET_ATMEL_USBA 247 at91_udp_hw_init(); 248 #endif 249 #ifdef CONFIG_GENERIC_ATMEL_MCI 250 sama5d3xek_mci_hw_init(); 251 #endif 252 #ifdef CONFIG_ATMEL_SPI 253 at91_spi0_hw_init(1 << 0); 254 #endif 255 #ifdef CONFIG_MACB 256 if (has_emac()) 257 at91_macb_hw_init(); 258 if (has_gmac()) 259 at91_gmac_hw_init(); 260 #endif 261 #ifdef CONFIG_LCD 262 if (has_lcdc()) 263 sama5d3xek_lcd_hw_init(); 264 #endif 265 return 0; 266 } 267 268 int dram_init(void) 269 { 270 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 271 CONFIG_SYS_SDRAM_SIZE); 272 return 0; 273 } 274 275 int board_phy_config(struct phy_device *phydev) 276 { 277 /* board specific timings for GMAC */ 278 if (has_gmac()) { 279 /* rx data delay */ 280 ksz9021_phy_extended_write(phydev, 281 MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 282 0x2222); 283 /* tx data delay */ 284 ksz9021_phy_extended_write(phydev, 285 MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 286 0x2222); 287 /* rx/tx clock delay */ 288 ksz9021_phy_extended_write(phydev, 289 MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 290 0xf2f4); 291 } 292 293 /* always run the PHY's config routine */ 294 if (phydev->drv->config) 295 return phydev->drv->config(phydev); 296 297 return 0; 298 } 299 300 int board_eth_init(bd_t *bis) 301 { 302 int rc = 0; 303 304 #ifdef CONFIG_MACB 305 if (has_emac()) 306 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); 307 if (has_gmac()) 308 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00); 309 #endif 310 #ifdef CONFIG_USB_GADGET_ATMEL_USBA 311 usba_udc_probe(&pdata); 312 #ifdef CONFIG_USB_ETH_RNDIS 313 usb_eth_initialize(bis); 314 #endif 315 #endif 316 317 return rc; 318 } 319 320 #ifdef CONFIG_GENERIC_ATMEL_MCI 321 int board_mmc_init(bd_t *bis) 322 { 323 int rc = 0; 324 325 rc = atmel_mci_init((void *)ATMEL_BASE_MCI0); 326 327 return rc; 328 } 329 #endif 330 331 /* SPI chip select control */ 332 #ifdef CONFIG_ATMEL_SPI 333 #include <spi.h> 334 335 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 336 { 337 return bus == 0 && cs < 4; 338 } 339 340 void spi_cs_activate(struct spi_slave *slave) 341 { 342 switch (slave->cs) { 343 case 0: 344 at91_set_pio_output(AT91_PIO_PORTD, 13, 0); 345 case 1: 346 at91_set_pio_output(AT91_PIO_PORTD, 14, 0); 347 case 2: 348 at91_set_pio_output(AT91_PIO_PORTD, 15, 0); 349 case 3: 350 at91_set_pio_output(AT91_PIO_PORTD, 16, 0); 351 default: 352 break; 353 } 354 } 355 356 void spi_cs_deactivate(struct spi_slave *slave) 357 { 358 switch (slave->cs) { 359 case 0: 360 at91_set_pio_output(AT91_PIO_PORTD, 13, 1); 361 case 1: 362 at91_set_pio_output(AT91_PIO_PORTD, 14, 1); 363 case 2: 364 at91_set_pio_output(AT91_PIO_PORTD, 15, 1); 365 case 3: 366 at91_set_pio_output(AT91_PIO_PORTD, 16, 1); 367 default: 368 break; 369 } 370 } 371 #endif /* CONFIG_ATMEL_SPI */ 372 373 #ifdef CONFIG_BOARD_LATE_INIT 374 int board_late_init(void) 375 { 376 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 377 const int MAX_STR_LEN = 32; 378 char name[MAX_STR_LEN], *p; 379 int i; 380 381 strncpy(name, get_cpu_name(), MAX_STR_LEN); 382 for (i = 0, p = name; (*p) && (i < MAX_STR_LEN); p++, i++) 383 *p = tolower(*p); 384 385 strcat(name, "ek.dtb"); 386 setenv("dtb_name", name); 387 #endif 388 return 0; 389 } 390 #endif 391 392 /* SPL */ 393 #ifdef CONFIG_SPL_BUILD 394 void spl_board_init(void) 395 { 396 #ifdef CONFIG_SYS_USE_MMC 397 sama5d3xek_mci_hw_init(); 398 #elif CONFIG_SYS_USE_NANDFLASH 399 sama5d3xek_nand_hw_init(); 400 #elif CONFIG_SYS_USE_SERIALFLASH 401 at91_spi0_hw_init(1 << 0); 402 #endif 403 } 404 405 static void ddr2_conf(struct atmel_mpddr *ddr2) 406 { 407 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); 408 409 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | 410 ATMEL_MPDDRC_CR_NR_ROW_14 | 411 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | 412 ATMEL_MPDDRC_CR_ENRDM_ON | 413 ATMEL_MPDDRC_CR_NB_8BANKS | 414 ATMEL_MPDDRC_CR_NDQS_DISABLED | 415 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | 416 ATMEL_MPDDRC_CR_UNAL_SUPPORTED); 417 /* 418 * As the DDR2-SDRAm device requires a refresh time is 7.8125us 419 * when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks 420 */ 421 ddr2->rtr = 0x411; 422 423 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | 424 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | 425 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | 426 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | 427 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | 428 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | 429 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | 430 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); 431 432 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | 433 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | 434 28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | 435 26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); 436 437 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | 438 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | 439 2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | 440 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | 441 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); 442 } 443 444 void mem_init(void) 445 { 446 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 447 struct atmel_mpddr ddr2; 448 449 ddr2_conf(&ddr2); 450 451 /* enable MPDDR clock */ 452 at91_periph_clk_enable(ATMEL_ID_MPDDRC); 453 writel(AT91_PMC_DDR, &pmc->scer); 454 455 /* DDRAM2 Controller initialize */ 456 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); 457 } 458 459 void at91_pmc_init(void) 460 { 461 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 462 u32 tmp; 463 464 tmp = AT91_PMC_PLLAR_29 | 465 AT91_PMC_PLLXR_PLLCOUNT(0x3f) | 466 AT91_PMC_PLLXR_MUL(43) | 467 AT91_PMC_PLLXR_DIV(1); 468 at91_plla_init(tmp); 469 470 writel(0x3 << 8, &pmc->pllicpr); 471 472 tmp = AT91_PMC_MCKR_MDIV_4 | 473 AT91_PMC_MCKR_CSS_PLLA; 474 at91_mck_init(tmp); 475 } 476 #endif 477