1 /*
2  * Copyright (C) 2012 - 2013 Atmel Corporation
3  * Bo Shen <voice.shen@atmel.com>
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #include <common.h>
9 #include <mmc.h>
10 #include <asm/io.h>
11 #include <asm/arch/sama5d3_smc.h>
12 #include <asm/arch/at91_common.h>
13 #include <asm/arch/at91_pmc.h>
14 #include <asm/arch/at91_rstc.h>
15 #include <asm/arch/gpio.h>
16 #include <asm/arch/clk.h>
17 #include <lcd.h>
18 #include <atmel_lcdc.h>
19 #include <atmel_mci.h>
20 #include <micrel.h>
21 #include <net.h>
22 #include <netdev.h>
23 #include <spl.h>
24 #include <asm/arch/atmel_mpddrc.h>
25 #include <asm/arch/at91_wdt.h>
26 
27 #ifdef CONFIG_USB_GADGET_ATMEL_USBA
28 #include <asm/arch/atmel_usba_udc.h>
29 #endif
30 
31 DECLARE_GLOBAL_DATA_PTR;
32 
33 /* ------------------------------------------------------------------------- */
34 /*
35  * Miscelaneous platform dependent initialisations
36  */
37 
38 #ifdef CONFIG_NAND_ATMEL
39 void sama5d3xek_nand_hw_init(void)
40 {
41 	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
42 
43 	at91_periph_clk_enable(ATMEL_ID_SMC);
44 
45 	/* Configure SMC CS3 for NAND/SmartMedia */
46 	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
47 	       AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
48 	       &smc->cs[3].setup);
49 	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
50 	       AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
51 	       &smc->cs[3].pulse);
52 	writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
53 	       &smc->cs[3].cycle);
54 	writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
55 	       AT91_SMC_TIMINGS_TAR(3)  | AT91_SMC_TIMINGS_TRR(4)   |
56 	       AT91_SMC_TIMINGS_TWB(5)  | AT91_SMC_TIMINGS_RBNSEL(3)|
57 	       AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
58 	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
59 	       AT91_SMC_MODE_EXNW_DISABLE |
60 #ifdef CONFIG_SYS_NAND_DBW_16
61 	       AT91_SMC_MODE_DBW_16 |
62 #else /* CONFIG_SYS_NAND_DBW_8 */
63 	       AT91_SMC_MODE_DBW_8 |
64 #endif
65 	       AT91_SMC_MODE_TDF_CYCLE(3),
66 	       &smc->cs[3].mode);
67 }
68 #endif
69 
70 #ifdef CONFIG_CMD_USB
71 static void sama5d3xek_usb_hw_init(void)
72 {
73 	at91_set_pio_output(AT91_PIO_PORTD, 25, 0);
74 	at91_set_pio_output(AT91_PIO_PORTD, 26, 0);
75 	at91_set_pio_output(AT91_PIO_PORTD, 27, 0);
76 }
77 #endif
78 
79 #ifdef CONFIG_GENERIC_ATMEL_MCI
80 static void sama5d3xek_mci_hw_init(void)
81 {
82 	at91_mci_hw_init();
83 
84 	at91_set_pio_output(AT91_PIO_PORTB, 10, 0);	/* MCI0 Power */
85 }
86 #endif
87 
88 #ifdef CONFIG_LCD
89 vidinfo_t panel_info = {
90 	.vl_col = 800,
91 	.vl_row = 480,
92 	.vl_clk = 24000000,
93 	.vl_sync = ATMEL_LCDC_INVLINE_NORMAL | ATMEL_LCDC_INVFRAME_NORMAL,
94 	.vl_bpix = LCD_BPP,
95 	.vl_tft = 1,
96 	.vl_hsync_len = 128,
97 	.vl_left_margin = 64,
98 	.vl_right_margin = 64,
99 	.vl_vsync_len = 2,
100 	.vl_upper_margin = 22,
101 	.vl_lower_margin = 21,
102 	.mmio = ATMEL_BASE_LCDC,
103 };
104 
105 void lcd_enable(void)
106 {
107 }
108 
109 void lcd_disable(void)
110 {
111 }
112 
113 static void sama5d3xek_lcd_hw_init(void)
114 {
115 	gd->fb_base = CONFIG_SAMA5D3_LCD_BASE;
116 
117 	/* The higher 8 bit of LCD is board related */
118 	at91_set_c_periph(AT91_PIO_PORTC, 14, 0);	/* LCDD16 */
119 	at91_set_c_periph(AT91_PIO_PORTC, 13, 0);	/* LCDD17 */
120 	at91_set_c_periph(AT91_PIO_PORTC, 12, 0);	/* LCDD18 */
121 	at91_set_c_periph(AT91_PIO_PORTC, 11, 0);	/* LCDD19 */
122 	at91_set_c_periph(AT91_PIO_PORTC, 10, 0);	/* LCDD20 */
123 	at91_set_c_periph(AT91_PIO_PORTC, 15, 0);	/* LCDD21 */
124 	at91_set_c_periph(AT91_PIO_PORTE, 27, 0);	/* LCDD22 */
125 	at91_set_c_periph(AT91_PIO_PORTE, 28, 0);	/* LCDD23 */
126 
127 	/* Configure lower 16 bit of LCD and enable clock */
128 	at91_lcd_hw_init();
129 }
130 
131 #ifdef CONFIG_LCD_INFO
132 #include <nand.h>
133 #include <version.h>
134 
135 void lcd_show_board_info(void)
136 {
137 	ulong dram_size;
138 	uint64_t nand_size;
139 	int i;
140 	char temp[32];
141 
142 	lcd_printf("%s\n", U_BOOT_VERSION);
143 	lcd_printf("(C) 2013 ATMEL Corp\n");
144 	lcd_printf("at91@atmel.com\n");
145 	lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
146 		   strmhz(temp, get_cpu_clk_rate()));
147 
148 	dram_size = 0;
149 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
150 		dram_size += gd->bd->bi_dram[i].size;
151 
152 	nand_size = 0;
153 #ifdef CONFIG_NAND_ATMEL
154 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
155 		nand_size += nand_info[i].size;
156 #endif
157 	lcd_printf("%ld MB SDRAM, %lld MB NAND\n",
158 		   dram_size >> 20, nand_size >> 20);
159 }
160 #endif /* CONFIG_LCD_INFO */
161 #endif /* CONFIG_LCD */
162 
163 int board_early_init_f(void)
164 {
165 	at91_periph_clk_enable(ATMEL_ID_PIOA);
166 	at91_periph_clk_enable(ATMEL_ID_PIOB);
167 	at91_periph_clk_enable(ATMEL_ID_PIOC);
168 	at91_periph_clk_enable(ATMEL_ID_PIOD);
169 	at91_periph_clk_enable(ATMEL_ID_PIOE);
170 
171 	at91_seriald_hw_init();
172 
173 	return 0;
174 }
175 
176 int board_init(void)
177 {
178 	/* adress of boot parameters */
179 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
180 
181 #ifdef CONFIG_NAND_ATMEL
182 	sama5d3xek_nand_hw_init();
183 #endif
184 #ifdef CONFIG_CMD_USB
185 	sama5d3xek_usb_hw_init();
186 #endif
187 #ifdef CONFIG_USB_GADGET_ATMEL_USBA
188 	at91_udp_hw_init();
189 #endif
190 #ifdef CONFIG_GENERIC_ATMEL_MCI
191 	sama5d3xek_mci_hw_init();
192 #endif
193 #ifdef CONFIG_ATMEL_SPI
194 	at91_spi0_hw_init(1 << 0);
195 #endif
196 #ifdef CONFIG_MACB
197 	if (has_emac())
198 		at91_macb_hw_init();
199 	if (has_gmac())
200 		at91_gmac_hw_init();
201 #endif
202 #ifdef CONFIG_LCD
203 	if (has_lcdc())
204 		sama5d3xek_lcd_hw_init();
205 #endif
206 	return 0;
207 }
208 
209 int dram_init(void)
210 {
211 	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
212 				    CONFIG_SYS_SDRAM_SIZE);
213 	return 0;
214 }
215 
216 int board_phy_config(struct phy_device *phydev)
217 {
218 	/* rx data delay */
219 	ksz9021_phy_extended_write(phydev,
220 				   MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x2222);
221 	/* tx data delay */
222 	ksz9021_phy_extended_write(phydev,
223 				   MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x2222);
224 	/* rx/tx clock delay */
225 	ksz9021_phy_extended_write(phydev,
226 				   MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf2f4);
227 
228 	return 0;
229 }
230 
231 int board_eth_init(bd_t *bis)
232 {
233 	int rc = 0;
234 
235 #ifdef CONFIG_MACB
236 	if (has_emac())
237 		rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
238 	if (has_gmac())
239 		rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
240 #endif
241 #ifdef CONFIG_USB_GADGET_ATMEL_USBA
242 	usba_udc_probe(&pdata);
243 #ifdef CONFIG_USB_ETH_RNDIS
244 	usb_eth_initialize(bis);
245 #endif
246 #endif
247 
248 	return rc;
249 }
250 
251 #ifdef CONFIG_GENERIC_ATMEL_MCI
252 int board_mmc_init(bd_t *bis)
253 {
254 	int rc = 0;
255 
256 	rc = atmel_mci_init((void *)ATMEL_BASE_MCI0);
257 
258 	return rc;
259 }
260 #endif
261 
262 /* SPI chip select control */
263 #ifdef CONFIG_ATMEL_SPI
264 #include <spi.h>
265 
266 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
267 {
268 	return bus == 0 && cs < 4;
269 }
270 
271 void spi_cs_activate(struct spi_slave *slave)
272 {
273 	switch (slave->cs) {
274 	case 0:
275 		at91_set_pio_output(AT91_PIO_PORTD, 13, 0);
276 	case 1:
277 		at91_set_pio_output(AT91_PIO_PORTD, 14, 0);
278 	case 2:
279 		at91_set_pio_output(AT91_PIO_PORTD, 15, 0);
280 	case 3:
281 		at91_set_pio_output(AT91_PIO_PORTD, 16, 0);
282 	default:
283 		break;
284 	}
285 }
286 
287 void spi_cs_deactivate(struct spi_slave *slave)
288 {
289 	switch (slave->cs) {
290 	case 0:
291 		at91_set_pio_output(AT91_PIO_PORTD, 13, 1);
292 	case 1:
293 		at91_set_pio_output(AT91_PIO_PORTD, 14, 1);
294 	case 2:
295 		at91_set_pio_output(AT91_PIO_PORTD, 15, 1);
296 	case 3:
297 		at91_set_pio_output(AT91_PIO_PORTD, 16, 1);
298 	default:
299 		break;
300 	}
301 }
302 #endif /* CONFIG_ATMEL_SPI */
303 
304 /* SPL */
305 #ifdef CONFIG_SPL_BUILD
306 void spl_board_init(void)
307 {
308 #ifdef CONFIG_SYS_USE_MMC
309 	sama5d3xek_mci_hw_init();
310 #elif CONFIG_SYS_USE_NANDFLASH
311 	sama5d3xek_nand_hw_init();
312 #elif CONFIG_SYS_USE_SERIALFLASH
313 	at91_spi0_hw_init(1 << 0);
314 #endif
315 }
316 
317 static void ddr2_conf(struct atmel_mpddr *ddr2)
318 {
319 	ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
320 
321 	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
322 		    ATMEL_MPDDRC_CR_NR_ROW_14 |
323 		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
324 		    ATMEL_MPDDRC_CR_ENRDM_ON |
325 		    ATMEL_MPDDRC_CR_NB_8BANKS |
326 		    ATMEL_MPDDRC_CR_NDQS_DISABLED |
327 		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
328 		    ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
329 	/*
330 	 * As the DDR2-SDRAm device requires a refresh time is 7.8125us
331 	 * when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks
332 	 */
333 	ddr2->rtr = 0x411;
334 
335 	ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
336 		      2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
337 		      2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
338 		      8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
339 		      2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
340 		      2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
341 		      2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
342 		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
343 
344 	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
345 		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
346 		      28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
347 		      26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
348 
349 	ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
350 		      2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
351 		      2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
352 		      7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
353 		      8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
354 }
355 
356 void mem_init(void)
357 {
358 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
359 	struct atmel_mpddr ddr2;
360 
361 	ddr2_conf(&ddr2);
362 
363 	/* enable MPDDR clock */
364 	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
365 	writel(0x4, &pmc->scer);
366 
367 	/* DDRAM2 Controller initialize */
368 	ddr2_init(ATMEL_BASE_DDRCS, &ddr2);
369 }
370 
371 void at91_pmc_init(void)
372 {
373 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
374 	u32 tmp;
375 
376 	tmp = AT91_PMC_PLLAR_29 |
377 	      AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
378 	      AT91_PMC_PLLXR_MUL(43) |
379 	      AT91_PMC_PLLXR_DIV(1);
380 	at91_plla_init(tmp);
381 
382 	writel(0x3 << 8, &pmc->pllicpr);
383 
384 	tmp = AT91_PMC_MCKR_MDIV_4 |
385 	      AT91_PMC_MCKR_CSS_PLLA;
386 	at91_mck_init(tmp);
387 }
388 #endif
389