1 /* 2 * Copyright (C) 2014 Atmel Corporation 3 * Bo Shen <voice.shen@atmel.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <asm/arch/sama5d3_smc.h> 11 #include <asm/arch/at91_common.h> 12 #include <asm/arch/at91_rstc.h> 13 #include <asm/arch/gpio.h> 14 #include <asm/arch/clk.h> 15 #include <debug_uart.h> 16 #include <spl.h> 17 #include <asm/arch/atmel_mpddrc.h> 18 #include <asm/arch/at91_wdt.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 #ifdef CONFIG_NAND_ATMEL 23 void sama5d3_xplained_nand_hw_init(void) 24 { 25 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 26 27 at91_periph_clk_enable(ATMEL_ID_SMC); 28 29 /* Configure SMC CS3 for NAND/SmartMedia */ 30 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) | 31 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1), 32 &smc->cs[3].setup); 33 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | 34 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5), 35 &smc->cs[3].pulse); 36 writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8), 37 &smc->cs[3].cycle); 38 writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) | 39 AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) | 40 AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3)| 41 AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); 42 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 43 AT91_SMC_MODE_EXNW_DISABLE | 44 #ifdef CONFIG_SYS_NAND_DBW_16 45 AT91_SMC_MODE_DBW_16 | 46 #else /* CONFIG_SYS_NAND_DBW_8 */ 47 AT91_SMC_MODE_DBW_8 | 48 #endif 49 AT91_SMC_MODE_TDF_CYCLE(3), 50 &smc->cs[3].mode); 51 } 52 #endif 53 54 #ifdef CONFIG_CMD_USB 55 static void sama5d3_xplained_usb_hw_init(void) 56 { 57 at91_set_pio_output(AT91_PIO_PORTE, 3, 0); 58 at91_set_pio_output(AT91_PIO_PORTE, 4, 0); 59 } 60 #endif 61 62 #ifdef CONFIG_GENERIC_ATMEL_MCI 63 static void sama5d3_xplained_mci0_hw_init(void) 64 { 65 at91_set_pio_output(AT91_PIO_PORTE, 2, 0); /* MCI0 Power */ 66 } 67 #endif 68 69 #ifdef CONFIG_DEBUG_UART_BOARD_INIT 70 void board_debug_uart_init(void) 71 { 72 at91_seriald_hw_init(); 73 } 74 #endif 75 76 #ifdef CONFIG_BOARD_EARLY_INIT_F 77 int board_early_init_f(void) 78 { 79 #ifdef CONFIG_DEBUG_UART 80 debug_uart_init(); 81 #endif 82 return 0; 83 } 84 #endif 85 86 int board_init(void) 87 { 88 /* adress of boot parameters */ 89 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 90 91 #ifdef CONFIG_NAND_ATMEL 92 sama5d3_xplained_nand_hw_init(); 93 #endif 94 #ifdef CONFIG_CMD_USB 95 sama5d3_xplained_usb_hw_init(); 96 #endif 97 #ifdef CONFIG_GENERIC_ATMEL_MCI 98 sama5d3_xplained_mci0_hw_init(); 99 #endif 100 return 0; 101 } 102 103 int dram_init(void) 104 { 105 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 106 CONFIG_SYS_SDRAM_SIZE); 107 108 return 0; 109 } 110 111 /* SPL */ 112 #ifdef CONFIG_SPL_BUILD 113 void spl_board_init(void) 114 { 115 #ifdef CONFIG_SYS_USE_MMC 116 #ifdef CONFIG_GENERIC_ATMEL_MCI 117 sama5d3_xplained_mci0_hw_init(); 118 #endif 119 #elif CONFIG_SYS_USE_NANDFLASH 120 sama5d3_xplained_nand_hw_init(); 121 #endif 122 } 123 124 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) 125 { 126 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); 127 128 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | 129 ATMEL_MPDDRC_CR_NR_ROW_14 | 130 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | 131 ATMEL_MPDDRC_CR_ENRDM_ON | 132 ATMEL_MPDDRC_CR_NB_8BANKS | 133 ATMEL_MPDDRC_CR_NDQS_DISABLED | 134 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | 135 ATMEL_MPDDRC_CR_UNAL_SUPPORTED); 136 /* 137 * As the DDR2-SDRAm device requires a refresh time is 7.8125us 138 * when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks 139 */ 140 ddr2->rtr = 0x411; 141 142 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | 143 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | 144 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | 145 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | 146 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | 147 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | 148 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | 149 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); 150 151 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | 152 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | 153 28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | 154 26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); 155 156 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | 157 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | 158 2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | 159 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | 160 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); 161 } 162 163 void mem_init(void) 164 { 165 struct atmel_mpddrc_config ddr2; 166 167 ddr2_conf(&ddr2); 168 169 /* Enable MPDDR clock */ 170 at91_periph_clk_enable(ATMEL_ID_MPDDRC); 171 at91_system_clk_enable(AT91_PMC_DDR); 172 173 /* DDRAM2 Controller initialize */ 174 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); 175 } 176 177 void at91_pmc_init(void) 178 { 179 u32 tmp; 180 181 tmp = AT91_PMC_PLLAR_29 | 182 AT91_PMC_PLLXR_PLLCOUNT(0x3f) | 183 AT91_PMC_PLLXR_MUL(43) | 184 AT91_PMC_PLLXR_DIV(1); 185 at91_plla_init(tmp); 186 187 at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3)); 188 189 tmp = AT91_PMC_MCKR_MDIV_4 | 190 AT91_PMC_MCKR_CSS_PLLA; 191 at91_mck_init(tmp); 192 } 193 #endif 194