1*7ca6f363SBo Shen /* 2*7ca6f363SBo Shen * Copyright (C) 2014 Atmel Corporation 3*7ca6f363SBo Shen * Bo Shen <voice.shen@atmel.com> 4*7ca6f363SBo Shen * 5*7ca6f363SBo Shen * SPDX-License-Identifier: GPL-2.0+ 6*7ca6f363SBo Shen */ 7*7ca6f363SBo Shen 8*7ca6f363SBo Shen #include <common.h> 9*7ca6f363SBo Shen #include <mmc.h> 10*7ca6f363SBo Shen #include <asm/io.h> 11*7ca6f363SBo Shen #include <asm/arch/sama5d3_smc.h> 12*7ca6f363SBo Shen #include <asm/arch/at91_common.h> 13*7ca6f363SBo Shen #include <asm/arch/at91_pmc.h> 14*7ca6f363SBo Shen #include <asm/arch/at91_rstc.h> 15*7ca6f363SBo Shen #include <asm/arch/gpio.h> 16*7ca6f363SBo Shen #include <asm/arch/clk.h> 17*7ca6f363SBo Shen #include <atmel_mci.h> 18*7ca6f363SBo Shen #include <net.h> 19*7ca6f363SBo Shen #include <netdev.h> 20*7ca6f363SBo Shen 21*7ca6f363SBo Shen DECLARE_GLOBAL_DATA_PTR; 22*7ca6f363SBo Shen 23*7ca6f363SBo Shen #ifdef CONFIG_NAND_ATMEL 24*7ca6f363SBo Shen void sama5d3_xplained_nand_hw_init(void) 25*7ca6f363SBo Shen { 26*7ca6f363SBo Shen struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 27*7ca6f363SBo Shen 28*7ca6f363SBo Shen at91_periph_clk_enable(ATMEL_ID_SMC); 29*7ca6f363SBo Shen 30*7ca6f363SBo Shen /* Configure SMC CS3 for NAND/SmartMedia */ 31*7ca6f363SBo Shen writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) | 32*7ca6f363SBo Shen AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1), 33*7ca6f363SBo Shen &smc->cs[3].setup); 34*7ca6f363SBo Shen writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | 35*7ca6f363SBo Shen AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5), 36*7ca6f363SBo Shen &smc->cs[3].pulse); 37*7ca6f363SBo Shen writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8), 38*7ca6f363SBo Shen &smc->cs[3].cycle); 39*7ca6f363SBo Shen writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) | 40*7ca6f363SBo Shen AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) | 41*7ca6f363SBo Shen AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3)| 42*7ca6f363SBo Shen AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); 43*7ca6f363SBo Shen writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 44*7ca6f363SBo Shen AT91_SMC_MODE_EXNW_DISABLE | 45*7ca6f363SBo Shen #ifdef CONFIG_SYS_NAND_DBW_16 46*7ca6f363SBo Shen AT91_SMC_MODE_DBW_16 | 47*7ca6f363SBo Shen #else /* CONFIG_SYS_NAND_DBW_8 */ 48*7ca6f363SBo Shen AT91_SMC_MODE_DBW_8 | 49*7ca6f363SBo Shen #endif 50*7ca6f363SBo Shen AT91_SMC_MODE_TDF_CYCLE(3), 51*7ca6f363SBo Shen &smc->cs[3].mode); 52*7ca6f363SBo Shen } 53*7ca6f363SBo Shen #endif 54*7ca6f363SBo Shen 55*7ca6f363SBo Shen #ifdef CONFIG_CMD_USB 56*7ca6f363SBo Shen static void sama5d3_xplained_usb_hw_init(void) 57*7ca6f363SBo Shen { 58*7ca6f363SBo Shen at91_set_pio_output(AT91_PIO_PORTE, 3, 0); 59*7ca6f363SBo Shen at91_set_pio_output(AT91_PIO_PORTE, 4, 0); 60*7ca6f363SBo Shen } 61*7ca6f363SBo Shen #endif 62*7ca6f363SBo Shen 63*7ca6f363SBo Shen #ifdef CONFIG_GENERIC_ATMEL_MCI 64*7ca6f363SBo Shen static void sama5d3_xplained_mci0_hw_init(void) 65*7ca6f363SBo Shen { 66*7ca6f363SBo Shen at91_mci_hw_init(); 67*7ca6f363SBo Shen 68*7ca6f363SBo Shen at91_set_pio_output(AT91_PIO_PORTE, 2, 0); /* MCI0 Power */ 69*7ca6f363SBo Shen } 70*7ca6f363SBo Shen #endif 71*7ca6f363SBo Shen 72*7ca6f363SBo Shen int board_early_init_f(void) 73*7ca6f363SBo Shen { 74*7ca6f363SBo Shen at91_periph_clk_enable(ATMEL_ID_PIOA); 75*7ca6f363SBo Shen at91_periph_clk_enable(ATMEL_ID_PIOB); 76*7ca6f363SBo Shen at91_periph_clk_enable(ATMEL_ID_PIOC); 77*7ca6f363SBo Shen at91_periph_clk_enable(ATMEL_ID_PIOD); 78*7ca6f363SBo Shen at91_periph_clk_enable(ATMEL_ID_PIOE); 79*7ca6f363SBo Shen 80*7ca6f363SBo Shen at91_seriald_hw_init(); 81*7ca6f363SBo Shen 82*7ca6f363SBo Shen return 0; 83*7ca6f363SBo Shen } 84*7ca6f363SBo Shen 85*7ca6f363SBo Shen int board_init(void) 86*7ca6f363SBo Shen { 87*7ca6f363SBo Shen /* adress of boot parameters */ 88*7ca6f363SBo Shen gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 89*7ca6f363SBo Shen 90*7ca6f363SBo Shen #ifdef CONFIG_NAND_ATMEL 91*7ca6f363SBo Shen sama5d3_xplained_nand_hw_init(); 92*7ca6f363SBo Shen #endif 93*7ca6f363SBo Shen #ifdef CONFIG_CMD_USB 94*7ca6f363SBo Shen sama5d3_xplained_usb_hw_init(); 95*7ca6f363SBo Shen #endif 96*7ca6f363SBo Shen #ifdef CONFIG_GENERIC_ATMEL_MCI 97*7ca6f363SBo Shen sama5d3_xplained_mci0_hw_init(); 98*7ca6f363SBo Shen #endif 99*7ca6f363SBo Shen #ifdef CONFIG_MACB 100*7ca6f363SBo Shen at91_gmac_hw_init(); 101*7ca6f363SBo Shen at91_macb_hw_init(); 102*7ca6f363SBo Shen #endif 103*7ca6f363SBo Shen return 0; 104*7ca6f363SBo Shen } 105*7ca6f363SBo Shen 106*7ca6f363SBo Shen int dram_init(void) 107*7ca6f363SBo Shen { 108*7ca6f363SBo Shen gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 109*7ca6f363SBo Shen CONFIG_SYS_SDRAM_SIZE); 110*7ca6f363SBo Shen 111*7ca6f363SBo Shen return 0; 112*7ca6f363SBo Shen } 113*7ca6f363SBo Shen 114*7ca6f363SBo Shen int board_eth_init(bd_t *bis) 115*7ca6f363SBo Shen { 116*7ca6f363SBo Shen #ifdef CONFIG_MACB 117*7ca6f363SBo Shen macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00); 118*7ca6f363SBo Shen macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); 119*7ca6f363SBo Shen #endif 120*7ca6f363SBo Shen return 0; 121*7ca6f363SBo Shen } 122*7ca6f363SBo Shen 123*7ca6f363SBo Shen #ifdef CONFIG_GENERIC_ATMEL_MCI 124*7ca6f363SBo Shen int board_mmc_init(bd_t *bis) 125*7ca6f363SBo Shen { 126*7ca6f363SBo Shen atmel_mci_init((void *)ATMEL_BASE_MCI0); 127*7ca6f363SBo Shen 128*7ca6f363SBo Shen return 0; 129*7ca6f363SBo Shen } 130*7ca6f363SBo Shen #endif 131