183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 27ca6f363SBo Shen /* 37ca6f363SBo Shen * Copyright (C) 2014 Atmel Corporation 47ca6f363SBo Shen * Bo Shen <voice.shen@atmel.com> 57ca6f363SBo Shen */ 67ca6f363SBo Shen 77ca6f363SBo Shen #include <common.h> 87ca6f363SBo Shen #include <asm/io.h> 97ca6f363SBo Shen #include <asm/arch/sama5d3_smc.h> 107ca6f363SBo Shen #include <asm/arch/at91_common.h> 117ca6f363SBo Shen #include <asm/arch/at91_rstc.h> 127ca6f363SBo Shen #include <asm/arch/gpio.h> 137ca6f363SBo Shen #include <asm/arch/clk.h> 14ad46af0eSWenyou Yang #include <debug_uart.h> 15cd23aac4SBo Shen #include <spl.h> 16cd23aac4SBo Shen #include <asm/arch/atmel_mpddrc.h> 17cd23aac4SBo Shen #include <asm/arch/at91_wdt.h> 187ca6f363SBo Shen 197ca6f363SBo Shen DECLARE_GLOBAL_DATA_PTR; 207ca6f363SBo Shen 21*59e43c32SEugen Hristev extern void at91_pda_detect(void); 22*59e43c32SEugen Hristev 237ca6f363SBo Shen #ifdef CONFIG_NAND_ATMEL 247ca6f363SBo Shen void sama5d3_xplained_nand_hw_init(void) 257ca6f363SBo Shen { 267ca6f363SBo Shen struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 277ca6f363SBo Shen 287ca6f363SBo Shen at91_periph_clk_enable(ATMEL_ID_SMC); 297ca6f363SBo Shen 307ca6f363SBo Shen /* Configure SMC CS3 for NAND/SmartMedia */ 317ca6f363SBo Shen writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) | 327ca6f363SBo Shen AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1), 337ca6f363SBo Shen &smc->cs[3].setup); 347ca6f363SBo Shen writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | 357ca6f363SBo Shen AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5), 367ca6f363SBo Shen &smc->cs[3].pulse); 377ca6f363SBo Shen writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8), 387ca6f363SBo Shen &smc->cs[3].cycle); 397ca6f363SBo Shen writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) | 407ca6f363SBo Shen AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) | 417ca6f363SBo Shen AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3)| 427ca6f363SBo Shen AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); 437ca6f363SBo Shen writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 447ca6f363SBo Shen AT91_SMC_MODE_EXNW_DISABLE | 457ca6f363SBo Shen #ifdef CONFIG_SYS_NAND_DBW_16 467ca6f363SBo Shen AT91_SMC_MODE_DBW_16 | 477ca6f363SBo Shen #else /* CONFIG_SYS_NAND_DBW_8 */ 487ca6f363SBo Shen AT91_SMC_MODE_DBW_8 | 497ca6f363SBo Shen #endif 507ca6f363SBo Shen AT91_SMC_MODE_TDF_CYCLE(3), 517ca6f363SBo Shen &smc->cs[3].mode); 527ca6f363SBo Shen } 537ca6f363SBo Shen #endif 547ca6f363SBo Shen 557ca6f363SBo Shen #ifdef CONFIG_CMD_USB 567ca6f363SBo Shen static void sama5d3_xplained_usb_hw_init(void) 577ca6f363SBo Shen { 587ca6f363SBo Shen at91_set_pio_output(AT91_PIO_PORTE, 3, 0); 597ca6f363SBo Shen at91_set_pio_output(AT91_PIO_PORTE, 4, 0); 607ca6f363SBo Shen } 617ca6f363SBo Shen #endif 627ca6f363SBo Shen 637ca6f363SBo Shen #ifdef CONFIG_GENERIC_ATMEL_MCI 647ca6f363SBo Shen static void sama5d3_xplained_mci0_hw_init(void) 657ca6f363SBo Shen { 667ca6f363SBo Shen at91_set_pio_output(AT91_PIO_PORTE, 2, 0); /* MCI0 Power */ 677ca6f363SBo Shen } 687ca6f363SBo Shen #endif 697ca6f363SBo Shen 70ad46af0eSWenyou Yang #ifdef CONFIG_DEBUG_UART_BOARD_INIT 71ad46af0eSWenyou Yang void board_debug_uart_init(void) 727ca6f363SBo Shen { 737ca6f363SBo Shen at91_seriald_hw_init(); 74ad46af0eSWenyou Yang } 75ad46af0eSWenyou Yang #endif 767ca6f363SBo Shen 77*59e43c32SEugen Hristev #ifdef CONFIG_BOARD_LATE_INIT 78*59e43c32SEugen Hristev int board_late_init(void) 79*59e43c32SEugen Hristev { 80*59e43c32SEugen Hristev at91_pda_detect(); 81*59e43c32SEugen Hristev return 0; 82*59e43c32SEugen Hristev } 83*59e43c32SEugen Hristev #endif 84*59e43c32SEugen Hristev 85ad46af0eSWenyou Yang #ifdef CONFIG_BOARD_EARLY_INIT_F 86ad46af0eSWenyou Yang int board_early_init_f(void) 87ad46af0eSWenyou Yang { 88ad46af0eSWenyou Yang #ifdef CONFIG_DEBUG_UART 89ad46af0eSWenyou Yang debug_uart_init(); 90ad46af0eSWenyou Yang #endif 917ca6f363SBo Shen return 0; 927ca6f363SBo Shen } 93ad46af0eSWenyou Yang #endif 947ca6f363SBo Shen 957ca6f363SBo Shen int board_init(void) 967ca6f363SBo Shen { 977ca6f363SBo Shen /* adress of boot parameters */ 987ca6f363SBo Shen gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 997ca6f363SBo Shen 1007ca6f363SBo Shen #ifdef CONFIG_NAND_ATMEL 1017ca6f363SBo Shen sama5d3_xplained_nand_hw_init(); 1027ca6f363SBo Shen #endif 1037ca6f363SBo Shen #ifdef CONFIG_CMD_USB 1047ca6f363SBo Shen sama5d3_xplained_usb_hw_init(); 1057ca6f363SBo Shen #endif 1067ca6f363SBo Shen #ifdef CONFIG_GENERIC_ATMEL_MCI 1077ca6f363SBo Shen sama5d3_xplained_mci0_hw_init(); 1087ca6f363SBo Shen #endif 1097ca6f363SBo Shen return 0; 1107ca6f363SBo Shen } 1117ca6f363SBo Shen 1127ca6f363SBo Shen int dram_init(void) 1137ca6f363SBo Shen { 1147ca6f363SBo Shen gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 1157ca6f363SBo Shen CONFIG_SYS_SDRAM_SIZE); 1167ca6f363SBo Shen 1177ca6f363SBo Shen return 0; 1187ca6f363SBo Shen } 1197ca6f363SBo Shen 120cd23aac4SBo Shen /* SPL */ 121cd23aac4SBo Shen #ifdef CONFIG_SPL_BUILD 122cd23aac4SBo Shen void spl_board_init(void) 123cd23aac4SBo Shen { 1245541543fSWenyou Yang #ifdef CONFIG_SD_BOOT 1251878804aSWenyou Yang #ifdef CONFIG_GENERIC_ATMEL_MCI 126cd23aac4SBo Shen sama5d3_xplained_mci0_hw_init(); 1271878804aSWenyou Yang #endif 1285541543fSWenyou Yang #elif CONFIG_NAND_BOOT 129cd23aac4SBo Shen sama5d3_xplained_nand_hw_init(); 130cd23aac4SBo Shen #endif 131cd23aac4SBo Shen } 132cd23aac4SBo Shen 1337e8702a0SWenyou Yang static void ddr2_conf(struct atmel_mpddrc_config *ddr2) 134cd23aac4SBo Shen { 135cd23aac4SBo Shen ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); 136cd23aac4SBo Shen 137cd23aac4SBo Shen ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | 138cd23aac4SBo Shen ATMEL_MPDDRC_CR_NR_ROW_14 | 139cd23aac4SBo Shen ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | 140cd23aac4SBo Shen ATMEL_MPDDRC_CR_ENRDM_ON | 141cd23aac4SBo Shen ATMEL_MPDDRC_CR_NB_8BANKS | 142cd23aac4SBo Shen ATMEL_MPDDRC_CR_NDQS_DISABLED | 143cd23aac4SBo Shen ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | 144cd23aac4SBo Shen ATMEL_MPDDRC_CR_UNAL_SUPPORTED); 145cd23aac4SBo Shen /* 146cd23aac4SBo Shen * As the DDR2-SDRAm device requires a refresh time is 7.8125us 147cd23aac4SBo Shen * when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks 148cd23aac4SBo Shen */ 149cd23aac4SBo Shen ddr2->rtr = 0x411; 150cd23aac4SBo Shen 151cd23aac4SBo Shen ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | 152cd23aac4SBo Shen 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | 153cd23aac4SBo Shen 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | 154cd23aac4SBo Shen 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | 155cd23aac4SBo Shen 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | 156cd23aac4SBo Shen 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | 157cd23aac4SBo Shen 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | 158cd23aac4SBo Shen 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); 159cd23aac4SBo Shen 160cd23aac4SBo Shen ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | 161cd23aac4SBo Shen 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | 162cd23aac4SBo Shen 28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | 163cd23aac4SBo Shen 26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); 164cd23aac4SBo Shen 165cd23aac4SBo Shen ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | 166cd23aac4SBo Shen 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | 167cd23aac4SBo Shen 2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | 168cd23aac4SBo Shen 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | 169cd23aac4SBo Shen 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); 170cd23aac4SBo Shen } 171cd23aac4SBo Shen 172cd23aac4SBo Shen void mem_init(void) 173cd23aac4SBo Shen { 1747e8702a0SWenyou Yang struct atmel_mpddrc_config ddr2; 175cd23aac4SBo Shen 176cd23aac4SBo Shen ddr2_conf(&ddr2); 177cd23aac4SBo Shen 17870341e2eSWenyou Yang /* Enable MPDDR clock */ 179cd23aac4SBo Shen at91_periph_clk_enable(ATMEL_ID_MPDDRC); 18070341e2eSWenyou Yang at91_system_clk_enable(AT91_PMC_DDR); 181cd23aac4SBo Shen 182cd23aac4SBo Shen /* DDRAM2 Controller initialize */ 1830c01c3e8SErik van Luijk ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); 184cd23aac4SBo Shen } 185cd23aac4SBo Shen 186cd23aac4SBo Shen void at91_pmc_init(void) 187cd23aac4SBo Shen { 188cd23aac4SBo Shen u32 tmp; 189cd23aac4SBo Shen 190cd23aac4SBo Shen tmp = AT91_PMC_PLLAR_29 | 191cd23aac4SBo Shen AT91_PMC_PLLXR_PLLCOUNT(0x3f) | 192cd23aac4SBo Shen AT91_PMC_PLLXR_MUL(43) | 193cd23aac4SBo Shen AT91_PMC_PLLXR_DIV(1); 194cd23aac4SBo Shen at91_plla_init(tmp); 195cd23aac4SBo Shen 196ede86ed2SWenyou Yang at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3)); 197cd23aac4SBo Shen 198cd23aac4SBo Shen tmp = AT91_PMC_MCKR_MDIV_4 | 199cd23aac4SBo Shen AT91_PMC_MCKR_CSS_PLLA; 200cd23aac4SBo Shen at91_mck_init(tmp); 201cd23aac4SBo Shen } 202cd23aac4SBo Shen #endif 203