1 /* 2 * Copyright (C) 2015 Atmel Corporation 3 * Wenyou.Yang <wenyou.yang@atmel.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <atmel_hlcdc.h> 10 #include <lcd.h> 11 #include <mmc.h> 12 #include <net.h> 13 #include <netdev.h> 14 #include <spi.h> 15 #include <version.h> 16 #include <asm/io.h> 17 #include <asm/arch/at91_common.h> 18 #include <asm/arch/atmel_pio4.h> 19 #include <asm/arch/atmel_mpddrc.h> 20 #include <asm/arch/atmel_usba_udc.h> 21 #include <asm/arch/atmel_sdhci.h> 22 #include <asm/arch/clk.h> 23 #include <asm/arch/gpio.h> 24 #include <asm/arch/sama5d2.h> 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 29 { 30 return bus == 0 && cs == 0; 31 } 32 33 void spi_cs_activate(struct spi_slave *slave) 34 { 35 atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 0); 36 } 37 38 void spi_cs_deactivate(struct spi_slave *slave) 39 { 40 atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1); 41 } 42 43 static void board_spi0_hw_init(void) 44 { 45 atmel_pio4_set_a_periph(AT91_PIO_PORTA, 14, 0); 46 atmel_pio4_set_a_periph(AT91_PIO_PORTA, 15, 0); 47 atmel_pio4_set_a_periph(AT91_PIO_PORTA, 16, 0); 48 49 atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1); 50 51 at91_periph_clk_enable(ATMEL_ID_SPI0); 52 } 53 54 static void board_usb_hw_init(void) 55 { 56 atmel_pio4_set_pio_output(AT91_PIO_PORTB, 10, 1); 57 } 58 59 #ifdef CONFIG_LCD 60 vidinfo_t panel_info = { 61 .vl_col = 480, 62 .vl_row = 272, 63 .vl_clk = 9000000, 64 .vl_bpix = LCD_BPP, 65 .vl_tft = 1, 66 .vl_hsync_len = 41, 67 .vl_left_margin = 2, 68 .vl_right_margin = 2, 69 .vl_vsync_len = 11, 70 .vl_upper_margin = 2, 71 .vl_lower_margin = 2, 72 .mmio = ATMEL_BASE_LCDC, 73 }; 74 75 /* No power up/down pin for the LCD pannel */ 76 void lcd_enable(void) { /* Empty! */ } 77 void lcd_disable(void) { /* Empty! */ } 78 79 unsigned int has_lcdc(void) 80 { 81 return 1; 82 } 83 84 static void board_lcd_hw_init(void) 85 { 86 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDPWM */ 87 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDISP */ 88 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDVSYNC */ 89 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 31, 0); /* LCDHSYNC */ 90 atmel_pio4_set_a_periph(AT91_PIO_PORTD, 0, 0); /* LCDPCK */ 91 atmel_pio4_set_a_periph(AT91_PIO_PORTD, 1, 0); /* LCDDEN */ 92 93 /* LCDDAT0 */ 94 /* LCDDAT1 */ 95 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDDAT2 */ 96 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDDAT3 */ 97 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDDAT4 */ 98 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDDAT5 */ 99 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDDAT6 */ 100 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDDAT7 */ 101 102 /* LCDDAT8 */ 103 /* LCDDAT9 */ 104 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDDAT10 */ 105 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDDAT11 */ 106 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDDAT12 */ 107 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDDAT13 */ 108 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDDAT14 */ 109 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDDAT15 */ 110 111 /* LCDD16 */ 112 /* LCDD17 */ 113 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDDAT18 */ 114 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDDAT19 */ 115 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDAT20 */ 116 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 25, 0); /* LCDDAT21 */ 117 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDDAT22 */ 118 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDDAT23 */ 119 120 at91_periph_clk_enable(ATMEL_ID_LCDC); 121 } 122 123 #ifdef CONFIG_LCD_INFO 124 void lcd_show_board_info(void) 125 { 126 ulong dram_size; 127 int i; 128 char temp[32]; 129 130 lcd_printf("%s\n", U_BOOT_VERSION); 131 lcd_printf("2015 ATMEL Corp\n"); 132 lcd_printf("%s CPU at %s MHz\n", get_cpu_name(), 133 strmhz(temp, get_cpu_clk_rate())); 134 135 dram_size = 0; 136 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 137 dram_size += gd->bd->bi_dram[i].size; 138 139 lcd_printf("%ld MB SDRAM\n", dram_size >> 20); 140 } 141 #endif /* CONFIG_LCD_INFO */ 142 #endif /* CONFIG_LCD */ 143 144 static void board_gmac_hw_init(void) 145 { 146 atmel_pio4_set_f_periph(AT91_PIO_PORTB, 14, 0); /* GTXCK */ 147 atmel_pio4_set_f_periph(AT91_PIO_PORTB, 15, 0); /* GTXEN */ 148 atmel_pio4_set_f_periph(AT91_PIO_PORTB, 16, 0); /* GRXDV */ 149 atmel_pio4_set_f_periph(AT91_PIO_PORTB, 17, 0); /* GRXER */ 150 atmel_pio4_set_f_periph(AT91_PIO_PORTB, 18, 0); /* GRX0 */ 151 atmel_pio4_set_f_periph(AT91_PIO_PORTB, 19, 0); /* GRX1 */ 152 atmel_pio4_set_f_periph(AT91_PIO_PORTB, 20, 0); /* GTX0 */ 153 atmel_pio4_set_f_periph(AT91_PIO_PORTB, 21, 0); /* GTX1 */ 154 atmel_pio4_set_f_periph(AT91_PIO_PORTB, 22, 0); /* GMDC */ 155 atmel_pio4_set_f_periph(AT91_PIO_PORTB, 23, 0); /* GMDIO */ 156 157 at91_periph_clk_enable(ATMEL_ID_GMAC); 158 } 159 160 static void board_sdhci0_hw_init(void) 161 { 162 atmel_pio4_set_a_periph(AT91_PIO_PORTA, 0, 0); /* SDMMC0_CK */ 163 atmel_pio4_set_a_periph(AT91_PIO_PORTA, 1, 0); /* SDMMC0_CMD */ 164 atmel_pio4_set_a_periph(AT91_PIO_PORTA, 2, 0); /* SDMMC0_DAT0 */ 165 atmel_pio4_set_a_periph(AT91_PIO_PORTA, 3, 0); /* SDMMC0_DAT1 */ 166 atmel_pio4_set_a_periph(AT91_PIO_PORTA, 4, 0); /* SDMMC0_DAT2 */ 167 atmel_pio4_set_a_periph(AT91_PIO_PORTA, 5, 0); /* SDMMC0_DAT3 */ 168 atmel_pio4_set_a_periph(AT91_PIO_PORTA, 6, 0); /* SDMMC0_DAT4 */ 169 atmel_pio4_set_a_periph(AT91_PIO_PORTA, 7, 0); /* SDMMC0_DAT5 */ 170 atmel_pio4_set_a_periph(AT91_PIO_PORTA, 8, 0); /* SDMMC0_DAT6 */ 171 atmel_pio4_set_a_periph(AT91_PIO_PORTA, 9, 0); /* SDMMC0_DAT7 */ 172 atmel_pio4_set_a_periph(AT91_PIO_PORTA, 10, 0); /* SDMMC0_RSTN */ 173 atmel_pio4_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SDMMC0_VDDSEL */ 174 atmel_pio4_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SDMMC0_CD */ 175 176 at91_periph_clk_enable(ATMEL_ID_SDMMC0); 177 at91_enable_periph_generated_clk(ATMEL_ID_SDMMC0, 178 GCK_CSS_UPLL_CLK, 1); 179 } 180 181 static void board_sdhci1_hw_init(void) 182 { 183 atmel_pio4_set_e_periph(AT91_PIO_PORTA, 18, 0); /* SDMMC1_DAT0 */ 184 atmel_pio4_set_e_periph(AT91_PIO_PORTA, 19, 0); /* SDMMC1_DAT1 */ 185 atmel_pio4_set_e_periph(AT91_PIO_PORTA, 20, 0); /* SDMMC1_DAT2 */ 186 atmel_pio4_set_e_periph(AT91_PIO_PORTA, 21, 0); /* SDMMC1_DAT3 */ 187 atmel_pio4_set_e_periph(AT91_PIO_PORTA, 22, 0); /* SDMMC1_CK */ 188 atmel_pio4_set_e_periph(AT91_PIO_PORTA, 27, 0); /* SDMMC1_RSTN */ 189 atmel_pio4_set_e_periph(AT91_PIO_PORTA, 28, 0); /* SDMMC1_CMD */ 190 atmel_pio4_set_e_periph(AT91_PIO_PORTA, 30, 0); /* SDMMC1_CD */ 191 192 at91_periph_clk_enable(ATMEL_ID_SDMMC1); 193 at91_enable_periph_generated_clk(ATMEL_ID_SDMMC1, 194 GCK_CSS_UPLL_CLK, 1); 195 } 196 197 int board_mmc_init(bd_t *bis) 198 { 199 #ifdef CONFIG_ATMEL_SDHCI0 200 atmel_sdhci_init((void *)ATMEL_BASE_SDMMC0, ATMEL_ID_SDMMC0); 201 #endif 202 #ifdef CONFIG_ATMEL_SDHCI1 203 atmel_sdhci_init((void *)ATMEL_BASE_SDMMC1, ATMEL_ID_SDMMC1); 204 #endif 205 206 return 0; 207 } 208 209 static void board_uart1_hw_init(void) 210 { 211 atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, 1); /* URXD1 */ 212 atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0); /* UTXD1 */ 213 214 at91_periph_clk_enable(ATMEL_ID_UART1); 215 } 216 217 int board_early_init_f(void) 218 { 219 at91_periph_clk_enable(ATMEL_ID_PIOA); 220 at91_periph_clk_enable(ATMEL_ID_PIOB); 221 at91_periph_clk_enable(ATMEL_ID_PIOC); 222 at91_periph_clk_enable(ATMEL_ID_PIOD); 223 224 board_uart1_hw_init(); 225 226 return 0; 227 } 228 229 int board_init(void) 230 { 231 /* address of boot parameters */ 232 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 233 234 #ifdef CONFIG_ATMEL_SPI 235 board_spi0_hw_init(); 236 #endif 237 #ifdef CONFIG_ATMEL_SDHCI 238 #ifdef CONFIG_ATMEL_SDHCI0 239 board_sdhci0_hw_init(); 240 #endif 241 #ifdef CONFIG_ATMEL_SDHCI1 242 board_sdhci1_hw_init(); 243 #endif 244 #endif 245 #ifdef CONFIG_MACB 246 board_gmac_hw_init(); 247 #endif 248 #ifdef CONFIG_LCD 249 board_lcd_hw_init(); 250 #endif 251 #ifdef CONFIG_CMD_USB 252 board_usb_hw_init(); 253 #endif 254 #ifdef CONFIG_USB_GADGET_ATMEL_USBA 255 at91_udp_hw_init(); 256 #endif 257 258 return 0; 259 } 260 261 int dram_init(void) 262 { 263 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 264 CONFIG_SYS_SDRAM_SIZE); 265 return 0; 266 } 267 268 int board_eth_init(bd_t *bis) 269 { 270 int rc = 0; 271 272 #ifdef CONFIG_MACB 273 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00); 274 #endif 275 276 #ifdef CONFIG_USB_GADGET_ATMEL_USBA 277 usba_udc_probe(&pdata); 278 #ifdef CONFIG_USB_ETH_RNDIS 279 usb_eth_initialize(bis); 280 #endif 281 #endif 282 283 return rc; 284 } 285 286 /* SPL */ 287 #ifdef CONFIG_SPL_BUILD 288 void spl_board_init(void) 289 { 290 #ifdef CONFIG_SYS_USE_SERIALFLASH 291 board_spi0_hw_init(); 292 #endif 293 #ifdef CONFIG_ATMEL_SDHCI 294 #ifdef CONFIG_ATMEL_SDHCI0 295 board_sdhci0_hw_init(); 296 #endif 297 #ifdef CONFIG_ATMEL_SDHCI1 298 board_sdhci1_hw_init(); 299 #endif 300 #endif 301 } 302 303 static void ddrc_conf(struct atmel_mpddrc_config *ddrc) 304 { 305 ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM); 306 307 ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | 308 ATMEL_MPDDRC_CR_NR_ROW_14 | 309 ATMEL_MPDDRC_CR_CAS_DDR_CAS5 | 310 ATMEL_MPDDRC_CR_DIC_DS | 311 ATMEL_MPDDRC_CR_DIS_DLL | 312 ATMEL_MPDDRC_CR_NB_8BANKS | 313 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | 314 ATMEL_MPDDRC_CR_UNAL_SUPPORTED); 315 316 ddrc->rtr = 0x511; 317 318 ddrc->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | 319 3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | 320 4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | 321 9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | 322 3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | 323 4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | 324 4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | 325 4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); 326 327 ddrc->tpr1 = (27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET | 328 29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | 329 0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | 330 3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET); 331 332 ddrc->tpr2 = (0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET | 333 0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | 334 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | 335 4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | 336 7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET); 337 } 338 339 void mem_init(void) 340 { 341 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 342 struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; 343 struct atmel_mpddrc_config ddrc_config; 344 u32 reg; 345 346 ddrc_conf(&ddrc_config); 347 348 at91_periph_clk_enable(ATMEL_ID_MPDDRC); 349 writel(AT91_PMC_DDR, &pmc->scer); 350 351 reg = readl(&mpddrc->io_calibr); 352 reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV; 353 reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55; 354 reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO; 355 reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100); 356 writel(reg, &mpddrc->io_calibr); 357 358 writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE, 359 &mpddrc->rd_data_path); 360 361 ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config); 362 363 writel(0x3, &mpddrc->cal_mr4); 364 writel(64, &mpddrc->tim_cal); 365 } 366 367 void at91_pmc_init(void) 368 { 369 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 370 u32 tmp; 371 372 tmp = AT91_PMC_PLLAR_29 | 373 AT91_PMC_PLLXR_PLLCOUNT(0x3f) | 374 AT91_PMC_PLLXR_MUL(82) | 375 AT91_PMC_PLLXR_DIV(1); 376 at91_plla_init(tmp); 377 378 writel(0x0 << 8, &pmc->pllicpr); 379 380 tmp = AT91_PMC_MCKR_H32MXDIV | 381 AT91_PMC_MCKR_PLLADIV_2 | 382 AT91_PMC_MCKR_MDIV_3 | 383 AT91_PMC_MCKR_CSS_PLLA; 384 at91_mck_init(tmp); 385 } 386 #endif 387