1 /* 2 * Copyright (C) 2015 Atmel Corporation 3 * Wenyou.Yang <wenyou.yang@atmel.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <atmel_hlcdc.h> 10 #include <debug_uart.h> 11 #include <dm.h> 12 #include <i2c.h> 13 #include <lcd.h> 14 #include <version.h> 15 #include <asm/io.h> 16 #include <asm/arch/at91_common.h> 17 #include <asm/arch/atmel_pio4.h> 18 #include <asm/arch/atmel_mpddrc.h> 19 #include <asm/arch/atmel_sdhci.h> 20 #include <asm/arch/clk.h> 21 #include <asm/arch/gpio.h> 22 #include <asm/arch/sama5d2.h> 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 static void board_usb_hw_init(void) 27 { 28 atmel_pio4_set_pio_output(AT91_PIO_PORTB, 10, 1); 29 } 30 31 #ifdef CONFIG_LCD 32 vidinfo_t panel_info = { 33 .vl_col = 480, 34 .vl_row = 272, 35 .vl_clk = 9000000, 36 .vl_bpix = LCD_BPP, 37 .vl_tft = 1, 38 .vl_hsync_len = 41, 39 .vl_left_margin = 2, 40 .vl_right_margin = 2, 41 .vl_vsync_len = 11, 42 .vl_upper_margin = 2, 43 .vl_lower_margin = 2, 44 .mmio = ATMEL_BASE_LCDC, 45 }; 46 47 /* No power up/down pin for the LCD pannel */ 48 void lcd_enable(void) { /* Empty! */ } 49 void lcd_disable(void) { /* Empty! */ } 50 51 unsigned int has_lcdc(void) 52 { 53 return 1; 54 } 55 56 static void board_lcd_hw_init(void) 57 { 58 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDPWM */ 59 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDISP */ 60 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDVSYNC */ 61 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 31, 0); /* LCDHSYNC */ 62 atmel_pio4_set_a_periph(AT91_PIO_PORTD, 0, 0); /* LCDPCK */ 63 atmel_pio4_set_a_periph(AT91_PIO_PORTD, 1, 0); /* LCDDEN */ 64 65 /* LCDDAT0 */ 66 /* LCDDAT1 */ 67 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDDAT2 */ 68 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDDAT3 */ 69 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDDAT4 */ 70 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDDAT5 */ 71 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDDAT6 */ 72 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDDAT7 */ 73 74 /* LCDDAT8 */ 75 /* LCDDAT9 */ 76 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDDAT10 */ 77 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDDAT11 */ 78 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDDAT12 */ 79 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDDAT13 */ 80 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDDAT14 */ 81 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDDAT15 */ 82 83 /* LCDD16 */ 84 /* LCDD17 */ 85 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDDAT18 */ 86 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDDAT19 */ 87 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDAT20 */ 88 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 25, 0); /* LCDDAT21 */ 89 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDDAT22 */ 90 atmel_pio4_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDDAT23 */ 91 92 at91_periph_clk_enable(ATMEL_ID_LCDC); 93 } 94 95 #ifdef CONFIG_LCD_INFO 96 void lcd_show_board_info(void) 97 { 98 ulong dram_size; 99 int i; 100 char temp[32]; 101 102 lcd_printf("%s\n", U_BOOT_VERSION); 103 lcd_printf("2015 ATMEL Corp\n"); 104 lcd_printf("%s CPU at %s MHz\n", get_cpu_name(), 105 strmhz(temp, get_cpu_clk_rate())); 106 107 dram_size = 0; 108 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 109 dram_size += gd->bd->bi_dram[i].size; 110 111 lcd_printf("%ld MB SDRAM\n", dram_size >> 20); 112 } 113 #endif /* CONFIG_LCD_INFO */ 114 #endif /* CONFIG_LCD */ 115 116 #ifdef CONFIG_DEBUG_UART_BOARD_INIT 117 static void board_uart1_hw_init(void) 118 { 119 atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, 1); /* URXD1 */ 120 atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0); /* UTXD1 */ 121 122 at91_periph_clk_enable(ATMEL_ID_UART1); 123 } 124 125 void board_debug_uart_init(void) 126 { 127 board_uart1_hw_init(); 128 } 129 #endif 130 131 #ifdef CONFIG_BOARD_EARLY_INIT_F 132 int board_early_init_f(void) 133 { 134 #ifdef CONFIG_DEBUG_UART 135 debug_uart_init(); 136 #endif 137 138 return 0; 139 } 140 #endif 141 142 int board_init(void) 143 { 144 /* address of boot parameters */ 145 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 146 147 #ifdef CONFIG_LCD 148 board_lcd_hw_init(); 149 #endif 150 #ifdef CONFIG_CMD_USB 151 board_usb_hw_init(); 152 #endif 153 154 return 0; 155 } 156 157 int dram_init(void) 158 { 159 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 160 CONFIG_SYS_SDRAM_SIZE); 161 return 0; 162 } 163 164 #ifdef CONFIG_CMD_I2C 165 static int set_ethaddr_from_eeprom(void) 166 { 167 const int ETH_ADDR_LEN = 6; 168 unsigned char ethaddr[ETH_ADDR_LEN]; 169 const char *ETHADDR_NAME = "ethaddr"; 170 struct udevice *bus, *dev; 171 172 if (getenv(ETHADDR_NAME)) 173 return 0; 174 175 if (uclass_get_device_by_seq(UCLASS_I2C, 1, &bus)) { 176 printf("Cannot find I2C bus 1\n"); 177 return -1; 178 } 179 180 if (dm_i2c_probe(bus, AT24MAC_ADDR, 0, &dev)) { 181 printf("Failed to probe I2C chip\n"); 182 return -1; 183 } 184 185 if (dm_i2c_read(dev, AT24MAC_REG, ethaddr, ETH_ADDR_LEN)) { 186 printf("Failed to read ethernet address from EEPROM\n"); 187 return -1; 188 } 189 190 if (!is_valid_ethaddr(ethaddr)) { 191 printf("The ethernet address read from EEPROM is not valid!\n"); 192 return -1; 193 } 194 195 return eth_setenv_enetaddr(ETHADDR_NAME, ethaddr); 196 } 197 #else 198 static int set_ethaddr_from_eeprom(void) 199 { 200 return 0; 201 } 202 #endif 203 204 #ifdef CONFIG_MISC_INIT_R 205 int misc_init_r(void) 206 { 207 set_ethaddr_from_eeprom(); 208 209 return 0; 210 } 211 #endif 212 213 /* SPL */ 214 #ifdef CONFIG_SPL_BUILD 215 void spl_board_init(void) 216 { 217 } 218 219 static void ddrc_conf(struct atmel_mpddrc_config *ddrc) 220 { 221 ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM); 222 223 ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | 224 ATMEL_MPDDRC_CR_NR_ROW_14 | 225 ATMEL_MPDDRC_CR_CAS_DDR_CAS5 | 226 ATMEL_MPDDRC_CR_DIC_DS | 227 ATMEL_MPDDRC_CR_DIS_DLL | 228 ATMEL_MPDDRC_CR_NB_8BANKS | 229 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | 230 ATMEL_MPDDRC_CR_UNAL_SUPPORTED); 231 232 ddrc->rtr = 0x511; 233 234 ddrc->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | 235 3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | 236 4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | 237 9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | 238 3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | 239 4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | 240 4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | 241 4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); 242 243 ddrc->tpr1 = (27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET | 244 29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | 245 0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | 246 3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET); 247 248 ddrc->tpr2 = (0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET | 249 0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | 250 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | 251 4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | 252 7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET); 253 } 254 255 void mem_init(void) 256 { 257 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 258 struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; 259 struct atmel_mpddrc_config ddrc_config; 260 u32 reg; 261 262 ddrc_conf(&ddrc_config); 263 264 at91_periph_clk_enable(ATMEL_ID_MPDDRC); 265 writel(AT91_PMC_DDR, &pmc->scer); 266 267 reg = readl(&mpddrc->io_calibr); 268 reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV; 269 reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55; 270 reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO; 271 reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100); 272 writel(reg, &mpddrc->io_calibr); 273 274 writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE, 275 &mpddrc->rd_data_path); 276 277 ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config); 278 279 writel(0x3, &mpddrc->cal_mr4); 280 writel(64, &mpddrc->tim_cal); 281 } 282 283 void at91_pmc_init(void) 284 { 285 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 286 u32 tmp; 287 288 tmp = AT91_PMC_PLLAR_29 | 289 AT91_PMC_PLLXR_PLLCOUNT(0x3f) | 290 AT91_PMC_PLLXR_MUL(82) | 291 AT91_PMC_PLLXR_DIV(1); 292 at91_plla_init(tmp); 293 294 writel(0x0 << 8, &pmc->pllicpr); 295 296 tmp = AT91_PMC_MCKR_H32MXDIV | 297 AT91_PMC_MCKR_PLLADIV_2 | 298 AT91_PMC_MCKR_MDIV_3 | 299 AT91_PMC_MCKR_CSS_PLLA; 300 at91_mck_init(tmp); 301 } 302 #endif 303