1 /* 2 * Copyright (C) 2017 Microchip Corporation 3 * Wenyou Yang <wenyou.yang@microchip.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <debug_uart.h> 10 #include <dm.h> 11 #include <i2c.h> 12 #include <nand.h> 13 #include <version.h> 14 #include <asm/io.h> 15 #include <asm/arch/at91_common.h> 16 #include <asm/arch/atmel_pio4.h> 17 #include <asm/arch/atmel_mpddrc.h> 18 #include <asm/arch/atmel_sdhci.h> 19 #include <asm/arch/clk.h> 20 #include <asm/arch/gpio.h> 21 #include <asm/arch/sama5d2.h> 22 #include <asm/arch/sama5d2_smc.h> 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 #ifdef CONFIG_NAND_ATMEL 27 static void board_nand_hw_init(void) 28 { 29 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 30 31 at91_periph_clk_enable(ATMEL_ID_HSMC); 32 33 /* Configure SMC CS3 for NAND */ 34 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | 35 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1), 36 &smc->cs[3].setup); 37 writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) | 38 AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3), 39 &smc->cs[3].pulse); 40 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), 41 &smc->cs[3].cycle); 42 writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) | 43 AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) | 44 AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3) | 45 AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); 46 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 47 AT91_SMC_MODE_EXNW_DISABLE | 48 AT91_SMC_MODE_DBW_8 | 49 AT91_SMC_MODE_TDF_CYCLE(3), 50 &smc->cs[3].mode); 51 52 atmel_pio4_set_b_periph(AT91_PIO_PORTA, 22, 0); /* D0 */ 53 atmel_pio4_set_b_periph(AT91_PIO_PORTA, 23, 0); /* D1 */ 54 atmel_pio4_set_b_periph(AT91_PIO_PORTA, 24, 0); /* D2 */ 55 atmel_pio4_set_b_periph(AT91_PIO_PORTA, 25, 0); /* D3 */ 56 atmel_pio4_set_b_periph(AT91_PIO_PORTA, 26, 0); /* D4 */ 57 atmel_pio4_set_b_periph(AT91_PIO_PORTA, 27, 0); /* D5 */ 58 atmel_pio4_set_b_periph(AT91_PIO_PORTA, 28, 0); /* D6 */ 59 atmel_pio4_set_b_periph(AT91_PIO_PORTA, 29, 0); /* D7 */ 60 atmel_pio4_set_b_periph(AT91_PIO_PORTB, 2, 0); /* RE */ 61 atmel_pio4_set_b_periph(AT91_PIO_PORTA, 30, 0); /* WE */ 62 atmel_pio4_set_b_periph(AT91_PIO_PORTA, 31, 1); /* NCS */ 63 atmel_pio4_set_b_periph(AT91_PIO_PORTC, 8, 1); /* RDY */ 64 atmel_pio4_set_b_periph(AT91_PIO_PORTB, 0, 1); /* ALE */ 65 atmel_pio4_set_b_periph(AT91_PIO_PORTB, 1, 1); /* CLE */ 66 } 67 #endif 68 69 static void board_usb_hw_init(void) 70 { 71 atmel_pio4_set_pio_output(AT91_PIO_PORTB, 12, 1); 72 } 73 74 #ifdef CONFIG_DEBUG_UART_BOARD_INIT 75 static void board_uart0_hw_init(void) 76 { 77 atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, 1); /* URXD0 */ 78 atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */ 79 80 at91_periph_clk_enable(ATMEL_ID_UART0); 81 } 82 83 void board_debug_uart_init(void) 84 { 85 board_uart0_hw_init(); 86 } 87 #endif 88 89 #ifdef CONFIG_BOARD_EARLY_INIT_F 90 int board_early_init_f(void) 91 { 92 #ifdef CONFIG_DEBUG_UART 93 debug_uart_init(); 94 #endif 95 return 0; 96 } 97 #endif 98 99 int board_init(void) 100 { 101 /* address of boot parameters */ 102 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 103 104 #ifdef CONFIG_NAND_ATMEL 105 board_nand_hw_init(); 106 #endif 107 #ifdef CONFIG_CMD_USB 108 board_usb_hw_init(); 109 #endif 110 return 0; 111 } 112 113 int dram_init(void) 114 { 115 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 116 CONFIG_SYS_SDRAM_SIZE); 117 return 0; 118 } 119 120 #define AT24MAC_MAC_OFFSET 0xfa 121 122 #ifdef CONFIG_MISC_INIT_R 123 int misc_init_r(void) 124 { 125 #ifdef CONFIG_I2C_EEPROM 126 at91_set_ethaddr(AT24MAC_MAC_OFFSET); 127 #endif 128 return 0; 129 } 130 #endif 131