1 /* 2 * Copyright (C) 2012 Atmel Corporation 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <asm/arch/at91sam9x5_matrix.h> 10 #include <asm/arch/at91sam9_smc.h> 11 #include <asm/arch/at91_common.h> 12 #include <asm/arch/at91_rstc.h> 13 #include <asm/arch/clk.h> 14 #include <asm/arch/gpio.h> 15 #include <debug_uart.h> 16 #include <lcd.h> 17 #include <atmel_hlcdc.h> 18 #ifdef CONFIG_LCD_INFO 19 #include <nand.h> 20 #include <version.h> 21 #endif 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 /* ------------------------------------------------------------------------- */ 26 /* 27 * Miscelaneous platform dependent initialisations 28 */ 29 #ifdef CONFIG_CMD_NAND 30 static void at91sam9x5ek_nand_hw_init(void) 31 { 32 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 33 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 34 unsigned long csa; 35 36 /* Enable CS3 */ 37 csa = readl(&matrix->ebicsa); 38 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; 39 /* NAND flash on D16 */ 40 csa |= AT91_MATRIX_NFD0_ON_D16; 41 42 /* Configure IO drive */ 43 csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL; 44 45 writel(csa, &matrix->ebicsa); 46 47 /* Configure SMC CS3 for NAND/SmartMedia */ 48 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | 49 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), 50 &smc->cs[3].setup); 51 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | 52 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6), 53 &smc->cs[3].pulse); 54 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6), 55 &smc->cs[3].cycle); 56 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 57 AT91_SMC_MODE_EXNW_DISABLE | 58 #ifdef CONFIG_SYS_NAND_DBW_16 59 AT91_SMC_MODE_DBW_16 | 60 #else /* CONFIG_SYS_NAND_DBW_8 */ 61 AT91_SMC_MODE_DBW_8 | 62 #endif 63 AT91_SMC_MODE_TDF_CYCLE(1), 64 &smc->cs[3].mode); 65 66 at91_periph_clk_enable(ATMEL_ID_PIOCD); 67 68 /* Configure RDY/BSY */ 69 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); 70 /* Enable NandFlash */ 71 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 72 73 at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ 74 at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ 75 at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */ 76 at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */ 77 at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1); 78 at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1); 79 at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1); 80 at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1); 81 at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1); 82 at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1); 83 at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1); 84 at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1); 85 } 86 #endif 87 88 #ifdef CONFIG_LCD 89 vidinfo_t panel_info = { 90 .vl_col = 800, 91 .vl_row = 480, 92 .vl_clk = 24000000, 93 .vl_sync = LCDC_LCDCFG5_HSPOL | LCDC_LCDCFG5_VSPOL, 94 .vl_bpix = LCD_BPP, 95 .vl_tft = 1, 96 .vl_clk_pol = 1, 97 .vl_hsync_len = 128, 98 .vl_left_margin = 64, 99 .vl_right_margin = 64, 100 .vl_vsync_len = 2, 101 .vl_upper_margin = 22, 102 .vl_lower_margin = 21, 103 .mmio = ATMEL_BASE_LCDC, 104 }; 105 106 void lcd_enable(void) 107 { 108 if (has_lcdc()) 109 at91_pio3_set_a_periph(AT91_PIO_PORTC, 29, 1); /* power up */ 110 } 111 112 void lcd_disable(void) 113 { 114 if (has_lcdc()) 115 at91_pio3_set_a_periph(AT91_PIO_PORTC, 29, 0); /* power down */ 116 } 117 118 static void at91sam9x5ek_lcd_hw_init(void) 119 { 120 if (has_lcdc()) { 121 at91_pio3_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDPWM */ 122 at91_pio3_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDVSYNC */ 123 at91_pio3_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDHSYNC */ 124 at91_pio3_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDISP */ 125 at91_pio3_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDEN */ 126 at91_pio3_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDPCK */ 127 128 at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDD0 */ 129 at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDD1 */ 130 at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDD2 */ 131 at91_pio3_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDD3 */ 132 at91_pio3_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD4 */ 133 at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD5 */ 134 at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD6 */ 135 at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD7 */ 136 at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD8 */ 137 at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD9 */ 138 at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD10 */ 139 at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD11 */ 140 at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDD12 */ 141 at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD13 */ 142 at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD14 */ 143 at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD15 */ 144 at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD16 */ 145 at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDD17 */ 146 at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD18 */ 147 at91_pio3_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD19 */ 148 at91_pio3_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD20 */ 149 at91_pio3_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD21 */ 150 at91_pio3_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */ 151 at91_pio3_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */ 152 153 at91_periph_clk_enable(ATMEL_ID_LCDC); 154 } 155 } 156 157 #ifdef CONFIG_LCD_INFO 158 void lcd_show_board_info(void) 159 { 160 ulong dram_size, nand_size; 161 int i; 162 char temp[32]; 163 164 if (has_lcdc()) { 165 lcd_printf("%s\n", U_BOOT_VERSION); 166 lcd_printf("(C) 2012 ATMEL Corp\n"); 167 lcd_printf("at91support@atmel.com\n"); 168 lcd_printf("%s CPU at %s MHz\n", 169 get_cpu_name(), 170 strmhz(temp, get_cpu_clk_rate())); 171 172 dram_size = 0; 173 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 174 dram_size += gd->bd->bi_dram[i].size; 175 nand_size = 0; 176 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 177 nand_size += nand_info[i]->size; 178 lcd_printf(" %ld MB SDRAM, %ld MB NAND\n", 179 dram_size >> 20, 180 nand_size >> 20); 181 } 182 } 183 #endif /* CONFIG_LCD_INFO */ 184 #endif /* CONFIG_LCD */ 185 186 #ifdef CONFIG_DEBUG_UART_BOARD_INIT 187 void board_debug_uart_init(void) 188 { 189 at91_seriald_hw_init(); 190 } 191 #endif 192 193 #ifdef CONFIG_BOARD_EARLY_INIT_F 194 int board_early_init_f(void) 195 { 196 #ifdef CONFIG_DEBUG_UART 197 debug_uart_init(); 198 #endif 199 return 0; 200 } 201 #endif 202 203 int board_init(void) 204 { 205 /* arch number of AT91SAM9X5EK-Board */ 206 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9X5EK; 207 208 /* adress of boot parameters */ 209 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 210 211 #ifdef CONFIG_CMD_NAND 212 at91sam9x5ek_nand_hw_init(); 213 #endif 214 215 #if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI_HCD) 216 at91_uhp_hw_init(); 217 #endif 218 #ifdef CONFIG_LCD 219 at91sam9x5ek_lcd_hw_init(); 220 #endif 221 return 0; 222 } 223 224 int dram_init(void) 225 { 226 gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE, 227 CONFIG_SYS_SDRAM_SIZE); 228 return 0; 229 } 230 231 #if defined(CONFIG_SPL_BUILD) 232 #include <spl.h> 233 #include <nand.h> 234 235 void at91_spl_board_init(void) 236 { 237 #ifdef CONFIG_SYS_USE_MMC 238 at91_mci_hw_init(); 239 #elif CONFIG_SYS_USE_NANDFLASH 240 at91sam9x5ek_nand_hw_init(); 241 #endif 242 } 243 244 #include <asm/arch/atmel_mpddrc.h> 245 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) 246 { 247 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); 248 249 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | 250 ATMEL_MPDDRC_CR_NR_ROW_13 | 251 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | 252 ATMEL_MPDDRC_CR_NB_8BANKS | 253 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED); 254 255 ddr2->rtr = 0x411; 256 257 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | 258 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | 259 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | 260 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | 261 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | 262 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | 263 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | 264 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); 265 266 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | 267 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | 268 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | 269 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); 270 271 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | 272 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | 273 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | 274 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | 275 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); 276 } 277 278 void mem_init(void) 279 { 280 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 281 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 282 struct atmel_mpddrc_config ddr2; 283 unsigned long csa; 284 285 ddr2_conf(&ddr2); 286 287 /* enable DDR2 clock */ 288 writel(AT91_PMC_DDR, &pmc->scer); 289 290 /* Chip select 1 is for DDR2/SDRAM */ 291 csa = readl(&matrix->ebicsa); 292 csa |= AT91_MATRIX_EBI_CS1A_SDRAMC; 293 csa &= ~AT91_MATRIX_EBI_DBPU_OFF; 294 csa |= AT91_MATRIX_EBI_DBPD_OFF; 295 csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL; 296 writel(csa, &matrix->ebicsa); 297 298 /* DDRAM2 Controller initialize */ 299 ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2); 300 } 301 #endif 302