1 /* 2 * Copyright (C) 2012 Atmel Corporation 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <asm/arch/at91sam9x5_matrix.h> 10 #include <asm/arch/at91sam9_smc.h> 11 #include <asm/arch/at91_common.h> 12 #include <asm/arch/at91_rstc.h> 13 #include <asm/arch/clk.h> 14 #include <asm/arch/gpio.h> 15 #include <debug_uart.h> 16 #include <lcd.h> 17 #include <atmel_hlcdc.h> 18 #ifdef CONFIG_LCD_INFO 19 #include <nand.h> 20 #include <version.h> 21 #endif 22 #include <asm/mach-types.h> 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 /* ------------------------------------------------------------------------- */ 27 /* 28 * Miscelaneous platform dependent initialisations 29 */ 30 #ifdef CONFIG_CMD_NAND 31 static void at91sam9x5ek_nand_hw_init(void) 32 { 33 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 34 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 35 unsigned long csa; 36 37 /* Enable CS3 */ 38 csa = readl(&matrix->ebicsa); 39 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; 40 /* NAND flash on D16 */ 41 csa |= AT91_MATRIX_NFD0_ON_D16; 42 43 /* Configure IO drive */ 44 csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL; 45 46 writel(csa, &matrix->ebicsa); 47 48 /* Configure SMC CS3 for NAND/SmartMedia */ 49 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | 50 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), 51 &smc->cs[3].setup); 52 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | 53 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6), 54 &smc->cs[3].pulse); 55 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6), 56 &smc->cs[3].cycle); 57 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 58 AT91_SMC_MODE_EXNW_DISABLE | 59 #ifdef CONFIG_SYS_NAND_DBW_16 60 AT91_SMC_MODE_DBW_16 | 61 #else /* CONFIG_SYS_NAND_DBW_8 */ 62 AT91_SMC_MODE_DBW_8 | 63 #endif 64 AT91_SMC_MODE_TDF_CYCLE(1), 65 &smc->cs[3].mode); 66 67 at91_periph_clk_enable(ATMEL_ID_PIOCD); 68 69 /* Configure RDY/BSY */ 70 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); 71 /* Enable NandFlash */ 72 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 73 74 at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ 75 at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ 76 at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */ 77 at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */ 78 at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1); 79 at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1); 80 at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1); 81 at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1); 82 at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1); 83 at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1); 84 at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1); 85 at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1); 86 } 87 #endif 88 89 #ifdef CONFIG_LCD 90 vidinfo_t panel_info = { 91 .vl_col = 800, 92 .vl_row = 480, 93 .vl_clk = 24000000, 94 .vl_sync = LCDC_LCDCFG5_HSPOL | LCDC_LCDCFG5_VSPOL, 95 .vl_bpix = LCD_BPP, 96 .vl_tft = 1, 97 .vl_clk_pol = 1, 98 .vl_hsync_len = 128, 99 .vl_left_margin = 64, 100 .vl_right_margin = 64, 101 .vl_vsync_len = 2, 102 .vl_upper_margin = 22, 103 .vl_lower_margin = 21, 104 .mmio = ATMEL_BASE_LCDC, 105 }; 106 107 void lcd_enable(void) 108 { 109 if (has_lcdc()) 110 at91_pio3_set_a_periph(AT91_PIO_PORTC, 29, 1); /* power up */ 111 } 112 113 void lcd_disable(void) 114 { 115 if (has_lcdc()) 116 at91_pio3_set_a_periph(AT91_PIO_PORTC, 29, 0); /* power down */ 117 } 118 119 static void at91sam9x5ek_lcd_hw_init(void) 120 { 121 if (has_lcdc()) { 122 at91_pio3_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDPWM */ 123 at91_pio3_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDVSYNC */ 124 at91_pio3_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDHSYNC */ 125 at91_pio3_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDISP */ 126 at91_pio3_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDEN */ 127 at91_pio3_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDPCK */ 128 129 at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDD0 */ 130 at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDD1 */ 131 at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDD2 */ 132 at91_pio3_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDD3 */ 133 at91_pio3_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD4 */ 134 at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD5 */ 135 at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD6 */ 136 at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD7 */ 137 at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD8 */ 138 at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD9 */ 139 at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD10 */ 140 at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD11 */ 141 at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDD12 */ 142 at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD13 */ 143 at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD14 */ 144 at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD15 */ 145 at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD16 */ 146 at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDD17 */ 147 at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD18 */ 148 at91_pio3_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD19 */ 149 at91_pio3_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD20 */ 150 at91_pio3_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD21 */ 151 at91_pio3_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */ 152 at91_pio3_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */ 153 154 at91_periph_clk_enable(ATMEL_ID_LCDC); 155 } 156 } 157 158 #ifdef CONFIG_LCD_INFO 159 void lcd_show_board_info(void) 160 { 161 ulong dram_size, nand_size; 162 int i; 163 char temp[32]; 164 165 if (has_lcdc()) { 166 lcd_printf("%s\n", U_BOOT_VERSION); 167 lcd_printf("(C) 2012 ATMEL Corp\n"); 168 lcd_printf("at91support@atmel.com\n"); 169 lcd_printf("%s CPU at %s MHz\n", 170 get_cpu_name(), 171 strmhz(temp, get_cpu_clk_rate())); 172 173 dram_size = 0; 174 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 175 dram_size += gd->bd->bi_dram[i].size; 176 nand_size = 0; 177 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 178 nand_size += get_nand_dev_by_index(i)->size; 179 lcd_printf(" %ld MB SDRAM, %ld MB NAND\n", 180 dram_size >> 20, 181 nand_size >> 20); 182 } 183 } 184 #endif /* CONFIG_LCD_INFO */ 185 #endif /* CONFIG_LCD */ 186 187 #ifdef CONFIG_DEBUG_UART_BOARD_INIT 188 void board_debug_uart_init(void) 189 { 190 at91_seriald_hw_init(); 191 } 192 #endif 193 194 #ifdef CONFIG_BOARD_EARLY_INIT_F 195 int board_early_init_f(void) 196 { 197 #ifdef CONFIG_DEBUG_UART 198 debug_uart_init(); 199 #endif 200 return 0; 201 } 202 #endif 203 204 int board_init(void) 205 { 206 /* arch number of AT91SAM9X5EK-Board */ 207 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9X5EK; 208 209 /* adress of boot parameters */ 210 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 211 212 #ifdef CONFIG_CMD_NAND 213 at91sam9x5ek_nand_hw_init(); 214 #endif 215 216 #if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI_HCD) 217 at91_uhp_hw_init(); 218 #endif 219 #ifdef CONFIG_LCD 220 at91sam9x5ek_lcd_hw_init(); 221 #endif 222 return 0; 223 } 224 225 int dram_init(void) 226 { 227 gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE, 228 CONFIG_SYS_SDRAM_SIZE); 229 return 0; 230 } 231 232 #if defined(CONFIG_SPL_BUILD) 233 #include <spl.h> 234 #include <nand.h> 235 236 void at91_spl_board_init(void) 237 { 238 #ifdef CONFIG_SD_BOOT 239 at91_mci_hw_init(); 240 #elif CONFIG_NAND_BOOT 241 at91sam9x5ek_nand_hw_init(); 242 #endif 243 } 244 245 #include <asm/arch/atmel_mpddrc.h> 246 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) 247 { 248 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); 249 250 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | 251 ATMEL_MPDDRC_CR_NR_ROW_13 | 252 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | 253 ATMEL_MPDDRC_CR_NB_8BANKS | 254 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED); 255 256 ddr2->rtr = 0x411; 257 258 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | 259 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | 260 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | 261 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | 262 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | 263 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | 264 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | 265 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); 266 267 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | 268 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | 269 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | 270 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); 271 272 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | 273 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | 274 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | 275 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | 276 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); 277 } 278 279 void mem_init(void) 280 { 281 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 282 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 283 struct atmel_mpddrc_config ddr2; 284 unsigned long csa; 285 286 ddr2_conf(&ddr2); 287 288 /* enable DDR2 clock */ 289 writel(AT91_PMC_DDR, &pmc->scer); 290 291 /* Chip select 1 is for DDR2/SDRAM */ 292 csa = readl(&matrix->ebicsa); 293 csa |= AT91_MATRIX_EBI_CS1A_SDRAMC; 294 csa &= ~AT91_MATRIX_EBI_DBPU_OFF; 295 csa |= AT91_MATRIX_EBI_DBPD_OFF; 296 csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL; 297 writel(csa, &matrix->ebicsa); 298 299 /* DDRAM2 Controller initialize */ 300 ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2); 301 } 302 #endif 303