1 /* 2 * Copyright (C) 2012 Atmel Corporation 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <asm/io.h> 25 #include <asm/arch/at91sam9x5_matrix.h> 26 #include <asm/arch/at91sam9_smc.h> 27 #include <asm/arch/at91_common.h> 28 #include <asm/arch/at91_pmc.h> 29 #include <asm/arch/at91_rstc.h> 30 #include <asm/arch/gpio.h> 31 #include <asm/arch/clk.h> 32 #include <lcd.h> 33 #include <atmel_hlcdc.h> 34 #include <atmel_mci.h> 35 #ifdef CONFIG_MACB 36 #include <net.h> 37 #endif 38 #include <netdev.h> 39 #ifdef CONFIG_LCD_INFO 40 #include <nand.h> 41 #include <version.h> 42 #endif 43 #ifdef CONFIG_ATMEL_SPI 44 #include <spi.h> 45 #endif 46 47 DECLARE_GLOBAL_DATA_PTR; 48 49 /* ------------------------------------------------------------------------- */ 50 /* 51 * Miscelaneous platform dependent initialisations 52 */ 53 #ifdef CONFIG_CMD_NAND 54 static void at91sam9x5ek_nand_hw_init(void) 55 { 56 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 57 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 58 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 59 unsigned long csa; 60 61 /* Enable CS3 */ 62 csa = readl(&matrix->ebicsa); 63 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; 64 /* NAND flash on D16 */ 65 csa |= AT91_MATRIX_NFD0_ON_D16; 66 67 /* Configure IO drive */ 68 csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL; 69 70 writel(csa, &matrix->ebicsa); 71 72 /* Configure SMC CS3 for NAND/SmartMedia */ 73 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | 74 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), 75 &smc->cs[3].setup); 76 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | 77 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6), 78 &smc->cs[3].pulse); 79 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6), 80 &smc->cs[3].cycle); 81 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 82 AT91_SMC_MODE_EXNW_DISABLE | 83 #ifdef CONFIG_SYS_NAND_DBW_16 84 AT91_SMC_MODE_DBW_16 | 85 #else /* CONFIG_SYS_NAND_DBW_8 */ 86 AT91_SMC_MODE_DBW_8 | 87 #endif 88 AT91_SMC_MODE_TDF_CYCLE(1), 89 &smc->cs[3].mode); 90 91 writel(1 << ATMEL_ID_PIOCD, &pmc->pcer); 92 93 /* Configure RDY/BSY */ 94 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); 95 /* Enable NandFlash */ 96 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 97 98 at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ 99 at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ 100 at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */ 101 at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */ 102 at91_set_a_periph(AT91_PIO_PORTD, 6, 1); 103 at91_set_a_periph(AT91_PIO_PORTD, 7, 1); 104 at91_set_a_periph(AT91_PIO_PORTD, 8, 1); 105 at91_set_a_periph(AT91_PIO_PORTD, 9, 1); 106 at91_set_a_periph(AT91_PIO_PORTD, 10, 1); 107 at91_set_a_periph(AT91_PIO_PORTD, 11, 1); 108 at91_set_a_periph(AT91_PIO_PORTD, 12, 1); 109 at91_set_a_periph(AT91_PIO_PORTD, 13, 1); 110 } 111 #endif 112 113 int board_eth_init(bd_t *bis) 114 { 115 int rc = 0; 116 117 #ifdef CONFIG_MACB 118 if (has_emac0()) 119 rc = macb_eth_initialize(0, 120 (void *)ATMEL_BASE_EMAC0, 0x00); 121 if (has_emac1()) 122 rc = macb_eth_initialize(1, 123 (void *)ATMEL_BASE_EMAC1, 0x00); 124 #endif 125 return rc; 126 } 127 128 #ifdef CONFIG_LCD 129 vidinfo_t panel_info = { 130 .vl_col = 800, 131 .vl_row = 480, 132 .vl_clk = 24000000, 133 .vl_sync = LCDC_LCDCFG5_HSPOL | LCDC_LCDCFG5_VSPOL, 134 .vl_bpix = LCD_BPP, 135 .vl_tft = 1, 136 .vl_clk_pol = 1, 137 .vl_hsync_len = 128, 138 .vl_left_margin = 64, 139 .vl_right_margin = 64, 140 .vl_vsync_len = 2, 141 .vl_upper_margin = 22, 142 .vl_lower_margin = 21, 143 .mmio = ATMEL_BASE_LCDC, 144 }; 145 146 void lcd_enable(void) 147 { 148 if (has_lcdc()) 149 at91_set_a_periph(AT91_PIO_PORTC, 29, 1); /* power up */ 150 } 151 152 void lcd_disable(void) 153 { 154 if (has_lcdc()) 155 at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* power down */ 156 } 157 158 static void at91sam9x5ek_lcd_hw_init(void) 159 { 160 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 161 162 if (has_lcdc()) { 163 at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDPWM */ 164 at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDVSYNC */ 165 at91_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDHSYNC */ 166 at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDISP */ 167 at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDEN */ 168 at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDPCK */ 169 170 at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDD0 */ 171 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDD1 */ 172 at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDD2 */ 173 at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDD3 */ 174 at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD4 */ 175 at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD5 */ 176 at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD6 */ 177 at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD7 */ 178 at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD8 */ 179 at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD9 */ 180 at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD10 */ 181 at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD11 */ 182 at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDD12 */ 183 at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD13 */ 184 at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD14 */ 185 at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD15 */ 186 at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD16 */ 187 at91_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDD17 */ 188 at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD18 */ 189 at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD19 */ 190 at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD20 */ 191 at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD21 */ 192 at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */ 193 at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */ 194 195 writel(1 << ATMEL_ID_LCDC, &pmc->pcer); 196 } 197 } 198 199 #ifdef CONFIG_LCD_INFO 200 void lcd_show_board_info(void) 201 { 202 ulong dram_size, nand_size; 203 int i; 204 char temp[32]; 205 206 if (has_lcdc()) { 207 lcd_printf("%s\n", U_BOOT_VERSION); 208 lcd_printf("(C) 2012 ATMEL Corp\n"); 209 lcd_printf("at91support@atmel.com\n"); 210 lcd_printf("%s CPU at %s MHz\n", 211 get_cpu_name(), 212 strmhz(temp, get_cpu_clk_rate())); 213 214 dram_size = 0; 215 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 216 dram_size += gd->bd->bi_dram[i].size; 217 nand_size = 0; 218 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 219 nand_size += nand_info[i].size; 220 lcd_printf(" %ld MB SDRAM, %ld MB NAND\n", 221 dram_size >> 20, 222 nand_size >> 20); 223 } 224 } 225 #endif /* CONFIG_LCD_INFO */ 226 #endif /* CONFIG_LCD */ 227 228 /* SPI chip select control */ 229 #ifdef CONFIG_ATMEL_SPI 230 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 231 { 232 return bus == 0 && cs < 2; 233 } 234 235 void spi_cs_activate(struct spi_slave *slave) 236 { 237 switch (slave->cs) { 238 case 1: 239 at91_set_pio_output(AT91_PIO_PORTA, 7, 0); 240 break; 241 case 0: 242 default: 243 at91_set_pio_output(AT91_PIO_PORTA, 14, 0); 244 break; 245 } 246 } 247 248 void spi_cs_deactivate(struct spi_slave *slave) 249 { 250 switch (slave->cs) { 251 case 1: 252 at91_set_pio_output(AT91_PIO_PORTA, 7, 1); 253 break; 254 case 0: 255 default: 256 at91_set_pio_output(AT91_PIO_PORTA, 14, 1); 257 break; 258 } 259 } 260 #endif /* CONFIG_ATMEL_SPI */ 261 262 #ifdef CONFIG_GENERIC_ATMEL_MCI 263 int board_mmc_init(bd_t *bd) 264 { 265 at91_mci_hw_init(); 266 267 return atmel_mci_init((void *)ATMEL_BASE_HSMCI0); 268 } 269 #endif 270 271 int board_early_init_f(void) 272 { 273 at91_seriald_hw_init(); 274 return 0; 275 } 276 277 int board_init(void) 278 { 279 /* arch number of AT91SAM9X5EK-Board */ 280 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9X5EK; 281 282 /* adress of boot parameters */ 283 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 284 285 #ifdef CONFIG_CMD_NAND 286 at91sam9x5ek_nand_hw_init(); 287 #endif 288 289 #ifdef CONFIG_ATMEL_SPI 290 at91_spi0_hw_init(1 << 0); 291 at91_spi0_hw_init(1 << 4); 292 #endif 293 294 #ifdef CONFIG_MACB 295 at91_macb_hw_init(); 296 #endif 297 298 #ifdef CONFIG_LCD 299 at91sam9x5ek_lcd_hw_init(); 300 #endif 301 return 0; 302 } 303 304 int dram_init(void) 305 { 306 gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE, 307 CONFIG_SYS_SDRAM_SIZE); 308 return 0; 309 } 310