1 /*
2  * Copyright (C) 2012 Atmel Corporation
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <asm/io.h>
9 #include <asm/arch/at91sam9x5_matrix.h>
10 #include <asm/arch/at91sam9_smc.h>
11 #include <asm/arch/at91_common.h>
12 #include <asm/arch/at91_pmc.h>
13 #include <asm/arch/at91_rstc.h>
14 #include <asm/arch/gpio.h>
15 #include <asm/arch/clk.h>
16 #include <lcd.h>
17 #include <atmel_hlcdc.h>
18 #include <atmel_mci.h>
19 #ifdef CONFIG_MACB
20 #include <net.h>
21 #endif
22 #include <netdev.h>
23 #ifdef CONFIG_LCD_INFO
24 #include <nand.h>
25 #include <version.h>
26 #endif
27 #ifdef CONFIG_ATMEL_SPI
28 #include <spi.h>
29 #endif
30 
31 DECLARE_GLOBAL_DATA_PTR;
32 
33 /* ------------------------------------------------------------------------- */
34 /*
35  * Miscelaneous platform dependent initialisations
36  */
37 #ifdef CONFIG_CMD_NAND
38 static void at91sam9x5ek_nand_hw_init(void)
39 {
40 	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
41 	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
42 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
43 	unsigned long csa;
44 
45 	/* Enable CS3 */
46 	csa = readl(&matrix->ebicsa);
47 	csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
48 	/* NAND flash on D16 */
49 	csa |= AT91_MATRIX_NFD0_ON_D16;
50 
51 	/* Configure IO drive */
52 	csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
53 
54 	writel(csa, &matrix->ebicsa);
55 
56 	/* Configure SMC CS3 for NAND/SmartMedia */
57 	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
58 		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
59 		&smc->cs[3].setup);
60 	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
61 		AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
62 		&smc->cs[3].pulse);
63 	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6),
64 		&smc->cs[3].cycle);
65 	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
66 		AT91_SMC_MODE_EXNW_DISABLE |
67 #ifdef CONFIG_SYS_NAND_DBW_16
68 		AT91_SMC_MODE_DBW_16 |
69 #else /* CONFIG_SYS_NAND_DBW_8 */
70 		AT91_SMC_MODE_DBW_8 |
71 #endif
72 		AT91_SMC_MODE_TDF_CYCLE(1),
73 		&smc->cs[3].mode);
74 
75 	writel(1 << ATMEL_ID_PIOCD, &pmc->pcer);
76 
77 	/* Configure RDY/BSY */
78 	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
79 	/* Enable NandFlash */
80 	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
81 
82 	at91_set_a_periph(AT91_PIO_PORTD, 0, 1);	/* NAND OE */
83 	at91_set_a_periph(AT91_PIO_PORTD, 1, 1);	/* NAND WE */
84 	at91_set_a_periph(AT91_PIO_PORTD, 2, 1);	/* NAND ALE */
85 	at91_set_a_periph(AT91_PIO_PORTD, 3, 1);	/* NAND CLE */
86 	at91_set_a_periph(AT91_PIO_PORTD, 6, 1);
87 	at91_set_a_periph(AT91_PIO_PORTD, 7, 1);
88 	at91_set_a_periph(AT91_PIO_PORTD, 8, 1);
89 	at91_set_a_periph(AT91_PIO_PORTD, 9, 1);
90 	at91_set_a_periph(AT91_PIO_PORTD, 10, 1);
91 	at91_set_a_periph(AT91_PIO_PORTD, 11, 1);
92 	at91_set_a_periph(AT91_PIO_PORTD, 12, 1);
93 	at91_set_a_periph(AT91_PIO_PORTD, 13, 1);
94 }
95 #endif
96 
97 int board_eth_init(bd_t *bis)
98 {
99 	int rc = 0;
100 
101 #ifdef CONFIG_MACB
102 	if (has_emac0())
103 		rc = macb_eth_initialize(0,
104 			(void *)ATMEL_BASE_EMAC0, 0x00);
105 	if (has_emac1())
106 		rc = macb_eth_initialize(1,
107 			(void *)ATMEL_BASE_EMAC1, 0x00);
108 #endif
109 	return rc;
110 }
111 
112 #ifdef CONFIG_LCD
113 vidinfo_t panel_info = {
114 	.vl_col	= 800,
115 	.vl_row = 480,
116 	.vl_clk = 24000000,
117 	.vl_sync = LCDC_LCDCFG5_HSPOL | LCDC_LCDCFG5_VSPOL,
118 	.vl_bpix = LCD_BPP,
119 	.vl_tft = 1,
120 	.vl_clk_pol = 1,
121 	.vl_hsync_len = 128,
122 	.vl_left_margin = 64,
123 	.vl_right_margin = 64,
124 	.vl_vsync_len = 2,
125 	.vl_upper_margin = 22,
126 	.vl_lower_margin = 21,
127 	.mmio = ATMEL_BASE_LCDC,
128 };
129 
130 void lcd_enable(void)
131 {
132 	if (has_lcdc())
133 		at91_set_a_periph(AT91_PIO_PORTC, 29, 1);	/* power up */
134 }
135 
136 void lcd_disable(void)
137 {
138 	if (has_lcdc())
139 		at91_set_a_periph(AT91_PIO_PORTC, 29, 0);	/* power down */
140 }
141 
142 static void at91sam9x5ek_lcd_hw_init(void)
143 {
144 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
145 
146 	if (has_lcdc()) {
147 		at91_set_a_periph(AT91_PIO_PORTC, 26, 0);	/* LCDPWM */
148 		at91_set_a_periph(AT91_PIO_PORTC, 27, 0);	/* LCDVSYNC */
149 		at91_set_a_periph(AT91_PIO_PORTC, 28, 0);	/* LCDHSYNC */
150 		at91_set_a_periph(AT91_PIO_PORTC, 24, 0);	/* LCDDISP */
151 		at91_set_a_periph(AT91_PIO_PORTC, 29, 0);	/* LCDDEN */
152 		at91_set_a_periph(AT91_PIO_PORTC, 30, 0);	/* LCDPCK */
153 
154 		at91_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* LCDD0 */
155 		at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* LCDD1 */
156 		at91_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* LCDD2 */
157 		at91_set_a_periph(AT91_PIO_PORTC, 3, 0);	/* LCDD3 */
158 		at91_set_a_periph(AT91_PIO_PORTC, 4, 0);	/* LCDD4 */
159 		at91_set_a_periph(AT91_PIO_PORTC, 5, 0);	/* LCDD5 */
160 		at91_set_a_periph(AT91_PIO_PORTC, 6, 0);	/* LCDD6 */
161 		at91_set_a_periph(AT91_PIO_PORTC, 7, 0);	/* LCDD7 */
162 		at91_set_a_periph(AT91_PIO_PORTC, 8, 0);	/* LCDD8 */
163 		at91_set_a_periph(AT91_PIO_PORTC, 9, 0);	/* LCDD9 */
164 		at91_set_a_periph(AT91_PIO_PORTC, 10, 0);	/* LCDD10 */
165 		at91_set_a_periph(AT91_PIO_PORTC, 11, 0);	/* LCDD11 */
166 		at91_set_a_periph(AT91_PIO_PORTC, 12, 0);	/* LCDD12 */
167 		at91_set_a_periph(AT91_PIO_PORTC, 13, 0);	/* LCDD13 */
168 		at91_set_a_periph(AT91_PIO_PORTC, 14, 0);	/* LCDD14 */
169 		at91_set_a_periph(AT91_PIO_PORTC, 15, 0);	/* LCDD15 */
170 		at91_set_a_periph(AT91_PIO_PORTC, 16, 0);	/* LCDD16 */
171 		at91_set_a_periph(AT91_PIO_PORTC, 17, 0);	/* LCDD17 */
172 		at91_set_a_periph(AT91_PIO_PORTC, 18, 0);	/* LCDD18 */
173 		at91_set_a_periph(AT91_PIO_PORTC, 19, 0);	/* LCDD19 */
174 		at91_set_a_periph(AT91_PIO_PORTC, 20, 0);	/* LCDD20 */
175 		at91_set_a_periph(AT91_PIO_PORTC, 21, 0);	/* LCDD21 */
176 		at91_set_a_periph(AT91_PIO_PORTC, 22, 0);	/* LCDD22 */
177 		at91_set_a_periph(AT91_PIO_PORTC, 23, 0);	/* LCDD23 */
178 
179 		writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
180 	}
181 }
182 
183 #ifdef CONFIG_LCD_INFO
184 void lcd_show_board_info(void)
185 {
186 	ulong dram_size, nand_size;
187 	int i;
188 	char temp[32];
189 
190 	if (has_lcdc()) {
191 		lcd_printf("%s\n", U_BOOT_VERSION);
192 		lcd_printf("(C) 2012 ATMEL Corp\n");
193 		lcd_printf("at91support@atmel.com\n");
194 		lcd_printf("%s CPU at %s MHz\n",
195 			get_cpu_name(),
196 			strmhz(temp, get_cpu_clk_rate()));
197 
198 		dram_size = 0;
199 		for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
200 			dram_size += gd->bd->bi_dram[i].size;
201 		nand_size = 0;
202 		for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
203 			nand_size += nand_info[i].size;
204 		lcd_printf("  %ld MB SDRAM, %ld MB NAND\n",
205 			dram_size >> 20,
206 			nand_size >> 20);
207 	}
208 }
209 #endif /* CONFIG_LCD_INFO */
210 #endif /* CONFIG_LCD */
211 
212 /* SPI chip select control */
213 #ifdef CONFIG_ATMEL_SPI
214 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
215 {
216 	return bus == 0 && cs < 2;
217 }
218 
219 void spi_cs_activate(struct spi_slave *slave)
220 {
221 	switch (slave->cs) {
222 	case 1:
223 		at91_set_pio_output(AT91_PIO_PORTA, 7, 0);
224 		break;
225 	case 0:
226 	default:
227 		at91_set_pio_output(AT91_PIO_PORTA, 14, 0);
228 		break;
229 	}
230 }
231 
232 void spi_cs_deactivate(struct spi_slave *slave)
233 {
234 	switch (slave->cs) {
235 	case 1:
236 		at91_set_pio_output(AT91_PIO_PORTA, 7, 1);
237 		break;
238 	case 0:
239 	default:
240 		at91_set_pio_output(AT91_PIO_PORTA, 14, 1);
241 		break;
242 	}
243 }
244 #endif /* CONFIG_ATMEL_SPI */
245 
246 #ifdef CONFIG_GENERIC_ATMEL_MCI
247 int board_mmc_init(bd_t *bd)
248 {
249 	at91_mci_hw_init();
250 
251 	return atmel_mci_init((void *)ATMEL_BASE_HSMCI0);
252 }
253 #endif
254 
255 int board_early_init_f(void)
256 {
257 	at91_seriald_hw_init();
258 	return 0;
259 }
260 
261 int board_init(void)
262 {
263 	/* arch number of AT91SAM9X5EK-Board */
264 	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9X5EK;
265 
266 	/* adress of boot parameters */
267 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
268 
269 #ifdef CONFIG_CMD_NAND
270 	at91sam9x5ek_nand_hw_init();
271 #endif
272 
273 #ifdef CONFIG_ATMEL_SPI
274 	at91_spi0_hw_init(1 << 4);
275 #endif
276 
277 #ifdef CONFIG_MACB
278 	at91_macb_hw_init();
279 #endif
280 
281 #if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI)
282 	at91_uhp_hw_init();
283 #endif
284 #ifdef CONFIG_LCD
285 	at91sam9x5ek_lcd_hw_init();
286 #endif
287 	return 0;
288 }
289 
290 int dram_init(void)
291 {
292 	gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
293 					CONFIG_SYS_SDRAM_SIZE);
294 	return 0;
295 }
296 
297 #if defined(CONFIG_SPL_BUILD)
298 #include <spl.h>
299 #include <nand.h>
300 
301 void at91_spl_board_init(void)
302 {
303 #ifdef CONFIG_SYS_USE_MMC
304 	at91_mci_hw_init();
305 #elif CONFIG_SYS_USE_NANDFLASH
306 	at91sam9x5ek_nand_hw_init();
307 #elif CONFIG_SYS_USE_SPIFLASH
308 	at91_spi0_hw_init(1 << 4);
309 #endif
310 }
311 
312 #include <asm/arch/atmel_mpddrc.h>
313 static void ddr2_conf(struct atmel_mpddr *ddr2)
314 {
315 	ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
316 
317 	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
318 		    ATMEL_MPDDRC_CR_NR_ROW_13 |
319 		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
320 		    ATMEL_MPDDRC_CR_NB_8BANKS |
321 		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
322 
323 	ddr2->rtr = 0x411;
324 
325 	ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
326 		      2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
327 		      2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
328 		      8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
329 		      2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
330 		      2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
331 		      2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
332 		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
333 
334 	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
335 		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
336 		      19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
337 		      18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
338 
339 	ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
340 		      2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
341 		      3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
342 		      7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
343 		      2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
344 }
345 
346 void mem_init(void)
347 {
348 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
349 	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
350 	struct atmel_mpddr ddr2;
351 	unsigned long csa;
352 
353 	ddr2_conf(&ddr2);
354 
355 	/* enable DDR2 clock */
356 	writel(0x4, &pmc->scer);
357 
358 	/* Chip select 1 is for DDR2/SDRAM */
359 	csa = readl(&matrix->ebicsa);
360 	csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
361 	csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
362 	csa |= AT91_MATRIX_EBI_DBPD_OFF;
363 	csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
364 	writel(csa, &matrix->ebicsa);
365 
366 	/* DDRAM2 Controller initialize */
367 	ddr2_init(ATMEL_BASE_CS1, &ddr2);
368 }
369 #endif
370