1 /*
2  * Copyright (C) 2012 Atmel Corporation
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <asm/io.h>
9 #include <asm/arch/at91sam9x5_matrix.h>
10 #include <asm/arch/at91sam9_smc.h>
11 #include <asm/arch/at91_common.h>
12 #include <asm/arch/at91_rstc.h>
13 #include <asm/arch/clk.h>
14 #include <asm/arch/gpio.h>
15 #include <lcd.h>
16 #include <atmel_hlcdc.h>
17 #include <atmel_mci.h>
18 #ifdef CONFIG_MACB
19 #include <net.h>
20 #endif
21 #include <netdev.h>
22 #ifdef CONFIG_LCD_INFO
23 #include <nand.h>
24 #include <version.h>
25 #endif
26 #ifdef CONFIG_ATMEL_SPI
27 #include <spi.h>
28 #endif
29 
30 DECLARE_GLOBAL_DATA_PTR;
31 
32 /* ------------------------------------------------------------------------- */
33 /*
34  * Miscelaneous platform dependent initialisations
35  */
36 #ifdef CONFIG_CMD_NAND
37 static void at91sam9x5ek_nand_hw_init(void)
38 {
39 	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
40 	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
41 	unsigned long csa;
42 
43 	/* Enable CS3 */
44 	csa = readl(&matrix->ebicsa);
45 	csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
46 	/* NAND flash on D16 */
47 	csa |= AT91_MATRIX_NFD0_ON_D16;
48 
49 	/* Configure IO drive */
50 	csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
51 
52 	writel(csa, &matrix->ebicsa);
53 
54 	/* Configure SMC CS3 for NAND/SmartMedia */
55 	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
56 		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
57 		&smc->cs[3].setup);
58 	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
59 		AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
60 		&smc->cs[3].pulse);
61 	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6),
62 		&smc->cs[3].cycle);
63 	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
64 		AT91_SMC_MODE_EXNW_DISABLE |
65 #ifdef CONFIG_SYS_NAND_DBW_16
66 		AT91_SMC_MODE_DBW_16 |
67 #else /* CONFIG_SYS_NAND_DBW_8 */
68 		AT91_SMC_MODE_DBW_8 |
69 #endif
70 		AT91_SMC_MODE_TDF_CYCLE(1),
71 		&smc->cs[3].mode);
72 
73 	at91_periph_clk_enable(ATMEL_ID_PIOCD);
74 
75 	/* Configure RDY/BSY */
76 	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
77 	/* Enable NandFlash */
78 	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
79 
80 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1);	/* NAND OE */
81 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1);	/* NAND WE */
82 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1);	/* NAND ALE */
83 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1);	/* NAND CLE */
84 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1);
85 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1);
86 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1);
87 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1);
88 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1);
89 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1);
90 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1);
91 	at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1);
92 }
93 #endif
94 
95 int board_eth_init(bd_t *bis)
96 {
97 	int rc = 0;
98 
99 #ifdef CONFIG_MACB
100 	if (has_emac0())
101 		rc = macb_eth_initialize(0,
102 			(void *)ATMEL_BASE_EMAC0, 0x00);
103 	if (has_emac1())
104 		rc = macb_eth_initialize(1,
105 			(void *)ATMEL_BASE_EMAC1, 0x00);
106 #endif
107 	return rc;
108 }
109 
110 #ifdef CONFIG_LCD
111 vidinfo_t panel_info = {
112 	.vl_col	= 800,
113 	.vl_row = 480,
114 	.vl_clk = 24000000,
115 	.vl_sync = LCDC_LCDCFG5_HSPOL | LCDC_LCDCFG5_VSPOL,
116 	.vl_bpix = LCD_BPP,
117 	.vl_tft = 1,
118 	.vl_clk_pol = 1,
119 	.vl_hsync_len = 128,
120 	.vl_left_margin = 64,
121 	.vl_right_margin = 64,
122 	.vl_vsync_len = 2,
123 	.vl_upper_margin = 22,
124 	.vl_lower_margin = 21,
125 	.mmio = ATMEL_BASE_LCDC,
126 };
127 
128 void lcd_enable(void)
129 {
130 	if (has_lcdc())
131 		at91_pio3_set_a_periph(AT91_PIO_PORTC, 29, 1);	/* power up */
132 }
133 
134 void lcd_disable(void)
135 {
136 	if (has_lcdc())
137 		at91_pio3_set_a_periph(AT91_PIO_PORTC, 29, 0);	/* power down */
138 }
139 
140 static void at91sam9x5ek_lcd_hw_init(void)
141 {
142 	if (has_lcdc()) {
143 		at91_pio3_set_a_periph(AT91_PIO_PORTC, 26, 0);	/* LCDPWM */
144 		at91_pio3_set_a_periph(AT91_PIO_PORTC, 27, 0);	/* LCDVSYNC */
145 		at91_pio3_set_a_periph(AT91_PIO_PORTC, 28, 0);	/* LCDHSYNC */
146 		at91_pio3_set_a_periph(AT91_PIO_PORTC, 24, 0);	/* LCDDISP */
147 		at91_pio3_set_a_periph(AT91_PIO_PORTC, 29, 0);	/* LCDDEN */
148 		at91_pio3_set_a_periph(AT91_PIO_PORTC, 30, 0);	/* LCDPCK */
149 
150 		at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* LCDD0 */
151 		at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* LCDD1 */
152 		at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* LCDD2 */
153 		at91_pio3_set_a_periph(AT91_PIO_PORTC, 3, 0);	/* LCDD3 */
154 		at91_pio3_set_a_periph(AT91_PIO_PORTC, 4, 0);	/* LCDD4 */
155 		at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0);	/* LCDD5 */
156 		at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0);	/* LCDD6 */
157 		at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0);	/* LCDD7 */
158 		at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0);	/* LCDD8 */
159 		at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0);	/* LCDD9 */
160 		at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0);	/* LCDD10 */
161 		at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0);	/* LCDD11 */
162 		at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0);	/* LCDD12 */
163 		at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0);	/* LCDD13 */
164 		at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0);	/* LCDD14 */
165 		at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 0);	/* LCDD15 */
166 		at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 0);	/* LCDD16 */
167 		at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 0);	/* LCDD17 */
168 		at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 0);	/* LCDD18 */
169 		at91_pio3_set_a_periph(AT91_PIO_PORTC, 19, 0);	/* LCDD19 */
170 		at91_pio3_set_a_periph(AT91_PIO_PORTC, 20, 0);	/* LCDD20 */
171 		at91_pio3_set_a_periph(AT91_PIO_PORTC, 21, 0);	/* LCDD21 */
172 		at91_pio3_set_a_periph(AT91_PIO_PORTC, 22, 0);	/* LCDD22 */
173 		at91_pio3_set_a_periph(AT91_PIO_PORTC, 23, 0);	/* LCDD23 */
174 
175 		at91_periph_clk_enable(ATMEL_ID_LCDC);
176 	}
177 }
178 
179 #ifdef CONFIG_LCD_INFO
180 void lcd_show_board_info(void)
181 {
182 	ulong dram_size, nand_size;
183 	int i;
184 	char temp[32];
185 
186 	if (has_lcdc()) {
187 		lcd_printf("%s\n", U_BOOT_VERSION);
188 		lcd_printf("(C) 2012 ATMEL Corp\n");
189 		lcd_printf("at91support@atmel.com\n");
190 		lcd_printf("%s CPU at %s MHz\n",
191 			get_cpu_name(),
192 			strmhz(temp, get_cpu_clk_rate()));
193 
194 		dram_size = 0;
195 		for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
196 			dram_size += gd->bd->bi_dram[i].size;
197 		nand_size = 0;
198 		for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
199 			nand_size += nand_info[i]->size;
200 		lcd_printf("  %ld MB SDRAM, %ld MB NAND\n",
201 			dram_size >> 20,
202 			nand_size >> 20);
203 	}
204 }
205 #endif /* CONFIG_LCD_INFO */
206 #endif /* CONFIG_LCD */
207 
208 /* SPI chip select control */
209 #ifdef CONFIG_ATMEL_SPI
210 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
211 {
212 	return bus == 0 && cs < 2;
213 }
214 
215 void spi_cs_activate(struct spi_slave *slave)
216 {
217 	switch (slave->cs) {
218 	case 1:
219 		at91_set_pio_output(AT91_PIO_PORTA, 7, 0);
220 		break;
221 	case 0:
222 	default:
223 		at91_set_pio_output(AT91_PIO_PORTA, 14, 0);
224 		break;
225 	}
226 }
227 
228 void spi_cs_deactivate(struct spi_slave *slave)
229 {
230 	switch (slave->cs) {
231 	case 1:
232 		at91_set_pio_output(AT91_PIO_PORTA, 7, 1);
233 		break;
234 	case 0:
235 	default:
236 		at91_set_pio_output(AT91_PIO_PORTA, 14, 1);
237 		break;
238 	}
239 }
240 #endif /* CONFIG_ATMEL_SPI */
241 
242 #ifdef CONFIG_GENERIC_ATMEL_MCI
243 int board_mmc_init(bd_t *bd)
244 {
245 	at91_mci_hw_init();
246 
247 	return atmel_mci_init((void *)ATMEL_BASE_HSMCI0);
248 }
249 #endif
250 
251 int board_early_init_f(void)
252 {
253 	at91_seriald_hw_init();
254 	return 0;
255 }
256 
257 int board_init(void)
258 {
259 	/* arch number of AT91SAM9X5EK-Board */
260 	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9X5EK;
261 
262 	/* adress of boot parameters */
263 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
264 
265 #ifdef CONFIG_CMD_NAND
266 	at91sam9x5ek_nand_hw_init();
267 #endif
268 
269 #ifdef CONFIG_ATMEL_SPI
270 	at91_spi0_hw_init(1 << 4);
271 #endif
272 
273 #ifdef CONFIG_MACB
274 	at91_macb_hw_init();
275 #endif
276 
277 #if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI)
278 	at91_uhp_hw_init();
279 #endif
280 #ifdef CONFIG_LCD
281 	at91sam9x5ek_lcd_hw_init();
282 #endif
283 	return 0;
284 }
285 
286 int dram_init(void)
287 {
288 	gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
289 					CONFIG_SYS_SDRAM_SIZE);
290 	return 0;
291 }
292 
293 #if defined(CONFIG_SPL_BUILD)
294 #include <spl.h>
295 #include <nand.h>
296 
297 void at91_spl_board_init(void)
298 {
299 #ifdef CONFIG_SYS_USE_MMC
300 	at91_mci_hw_init();
301 #elif CONFIG_SYS_USE_NANDFLASH
302 	at91sam9x5ek_nand_hw_init();
303 #elif CONFIG_SYS_USE_SPIFLASH
304 	at91_spi0_hw_init(1 << 4);
305 #endif
306 }
307 
308 #include <asm/arch/atmel_mpddrc.h>
309 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
310 {
311 	ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
312 
313 	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
314 		    ATMEL_MPDDRC_CR_NR_ROW_13 |
315 		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
316 		    ATMEL_MPDDRC_CR_NB_8BANKS |
317 		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
318 
319 	ddr2->rtr = 0x411;
320 
321 	ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
322 		      2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
323 		      2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
324 		      8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
325 		      2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
326 		      2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
327 		      2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
328 		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
329 
330 	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
331 		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
332 		      19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
333 		      18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
334 
335 	ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
336 		      2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
337 		      3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
338 		      7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
339 		      2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
340 }
341 
342 void mem_init(void)
343 {
344 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
345 	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
346 	struct atmel_mpddrc_config ddr2;
347 	unsigned long csa;
348 
349 	ddr2_conf(&ddr2);
350 
351 	/* enable DDR2 clock */
352 	writel(AT91_PMC_DDR, &pmc->scer);
353 
354 	/* Chip select 1 is for DDR2/SDRAM */
355 	csa = readl(&matrix->ebicsa);
356 	csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
357 	csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
358 	csa |= AT91_MATRIX_EBI_DBPD_OFF;
359 	csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
360 	writel(csa, &matrix->ebicsa);
361 
362 	/* DDRAM2 Controller initialize */
363 	ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);
364 }
365 #endif
366