1 /* 2 * Copyright (C) 2012 Atmel Corporation 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <asm/io.h> 25 #include <asm/arch/at91sam9x5_matrix.h> 26 #include <asm/arch/at91sam9_smc.h> 27 #include <asm/arch/at91_common.h> 28 #include <asm/arch/at91_pmc.h> 29 #include <asm/arch/at91_rstc.h> 30 #include <asm/arch/gpio.h> 31 #include <asm/arch/clk.h> 32 #include <lcd.h> 33 #include <atmel_hlcdc.h> 34 #ifdef CONFIG_MACB 35 #include <net.h> 36 #endif 37 #include <netdev.h> 38 #ifdef CONFIG_LCD_INFO 39 #include <nand.h> 40 #include <version.h> 41 #endif 42 #ifdef CONFIG_ATMEL_SPI 43 #include <spi.h> 44 #endif 45 46 DECLARE_GLOBAL_DATA_PTR; 47 48 /* ------------------------------------------------------------------------- */ 49 /* 50 * Miscelaneous platform dependent initialisations 51 */ 52 #ifdef CONFIG_CMD_NAND 53 static void at91sam9x5ek_nand_hw_init(void) 54 { 55 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 56 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 57 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 58 unsigned long csa; 59 60 /* Enable CS3 */ 61 csa = readl(&matrix->ebicsa); 62 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; 63 writel(csa, &matrix->ebicsa); 64 65 /* Configure SMC CS3 for NAND/SmartMedia */ 66 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | 67 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), 68 &smc->cs[3].setup); 69 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) | 70 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4), 71 &smc->cs[3].pulse); 72 writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7), 73 &smc->cs[3].cycle); 74 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 75 AT91_SMC_MODE_EXNW_DISABLE | 76 #ifdef CONFIG_SYS_NAND_DBW_16 77 AT91_SMC_MODE_DBW_16 | 78 #else /* CONFIG_SYS_NAND_DBW_8 */ 79 AT91_SMC_MODE_DBW_8 | 80 #endif 81 AT91_SMC_MODE_TDF_CYCLE(3), 82 &smc->cs[3].mode); 83 84 writel(1 << ATMEL_ID_PIOCD, &pmc->pcer); 85 86 /* Configure RDY/BSY */ 87 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); 88 /* Enable NandFlash */ 89 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 90 91 at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ 92 at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ 93 at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */ 94 at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */ 95 at91_set_a_periph(AT91_PIO_PORTD, 6, 1); 96 at91_set_a_periph(AT91_PIO_PORTD, 7, 1); 97 at91_set_a_periph(AT91_PIO_PORTD, 8, 1); 98 at91_set_a_periph(AT91_PIO_PORTD, 9, 1); 99 at91_set_a_periph(AT91_PIO_PORTD, 10, 1); 100 at91_set_a_periph(AT91_PIO_PORTD, 11, 1); 101 at91_set_a_periph(AT91_PIO_PORTD, 12, 1); 102 at91_set_a_periph(AT91_PIO_PORTD, 13, 1); 103 } 104 #endif 105 106 int board_eth_init(bd_t *bis) 107 { 108 int rc = 0; 109 110 #ifdef CONFIG_MACB 111 if (has_emac0()) 112 rc = macb_eth_initialize(0, 113 (void *)ATMEL_BASE_EMAC0, 0x00); 114 if (has_emac1()) 115 rc = macb_eth_initialize(1, 116 (void *)ATMEL_BASE_EMAC1, 0x00); 117 #endif 118 return rc; 119 } 120 121 #ifdef CONFIG_LCD 122 vidinfo_t panel_info = { 123 .vl_col = 800, 124 .vl_row = 480, 125 .vl_clk = 24000000, 126 .vl_sync = LCDC_LCDCFG5_HSPOL | LCDC_LCDCFG5_VSPOL, 127 .vl_bpix = LCD_BPP, 128 .vl_tft = 1, 129 .vl_clk_pol = 1, 130 .vl_hsync_len = 128, 131 .vl_left_margin = 64, 132 .vl_right_margin = 64, 133 .vl_vsync_len = 2, 134 .vl_upper_margin = 22, 135 .vl_lower_margin = 21, 136 .mmio = ATMEL_BASE_LCDC, 137 }; 138 139 void lcd_enable(void) 140 { 141 if (has_lcdc()) 142 at91_set_a_periph(AT91_PIO_PORTC, 29, 1); /* power up */ 143 } 144 145 void lcd_disable(void) 146 { 147 if (has_lcdc()) 148 at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* power down */ 149 } 150 151 static void at91sam9x5ek_lcd_hw_init(void) 152 { 153 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 154 155 if (has_lcdc()) { 156 at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDPWM */ 157 at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDVSYNC */ 158 at91_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDHSYNC */ 159 at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDISP */ 160 at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDEN */ 161 at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDPCK */ 162 163 at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDD0 */ 164 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDD1 */ 165 at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDD2 */ 166 at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDD3 */ 167 at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD4 */ 168 at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD5 */ 169 at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD6 */ 170 at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD7 */ 171 at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD8 */ 172 at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD9 */ 173 at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD10 */ 174 at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD11 */ 175 at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDD12 */ 176 at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD13 */ 177 at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD14 */ 178 at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD15 */ 179 at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD16 */ 180 at91_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDD17 */ 181 at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD18 */ 182 at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD19 */ 183 at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD20 */ 184 at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD21 */ 185 at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */ 186 at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */ 187 188 writel(1 << ATMEL_ID_LCDC, &pmc->pcer); 189 } 190 } 191 192 #ifdef CONFIG_LCD_INFO 193 void lcd_show_board_info(void) 194 { 195 ulong dram_size, nand_size; 196 int i; 197 char temp[32]; 198 199 if (has_lcdc()) { 200 lcd_printf("%s\n", U_BOOT_VERSION); 201 lcd_printf("(C) 2012 ATMEL Corp\n"); 202 lcd_printf("at91support@atmel.com\n"); 203 lcd_printf("%s CPU at %s MHz\n", 204 get_cpu_name(), 205 strmhz(temp, get_cpu_clk_rate())); 206 207 dram_size = 0; 208 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 209 dram_size += gd->bd->bi_dram[i].size; 210 nand_size = 0; 211 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 212 nand_size += nand_info[i].size; 213 lcd_printf(" %ld MB SDRAM, %ld MB NAND\n", 214 dram_size >> 20, 215 nand_size >> 20); 216 } 217 } 218 #endif /* CONFIG_LCD_INFO */ 219 #endif /* CONFIG_LCD */ 220 221 /* SPI chip select control */ 222 #ifdef CONFIG_ATMEL_SPI 223 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 224 { 225 return bus == 0 && cs < 2; 226 } 227 228 void spi_cs_activate(struct spi_slave *slave) 229 { 230 switch (slave->cs) { 231 case 1: 232 at91_set_pio_output(AT91_PIO_PORTA, 7, 0); 233 break; 234 case 0: 235 default: 236 at91_set_pio_output(AT91_PIO_PORTA, 14, 0); 237 break; 238 } 239 } 240 241 void spi_cs_deactivate(struct spi_slave *slave) 242 { 243 switch (slave->cs) { 244 case 1: 245 at91_set_pio_output(AT91_PIO_PORTA, 7, 1); 246 break; 247 case 0: 248 default: 249 at91_set_pio_output(AT91_PIO_PORTA, 14, 1); 250 break; 251 } 252 } 253 #endif /* CONFIG_ATMEL_SPI */ 254 255 int board_early_init_f(void) 256 { 257 at91_seriald_hw_init(); 258 return 0; 259 } 260 261 int board_init(void) 262 { 263 /* arch number of AT91SAM9X5EK-Board */ 264 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9X5EK; 265 266 /* adress of boot parameters */ 267 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 268 269 #ifdef CONFIG_CMD_NAND 270 at91sam9x5ek_nand_hw_init(); 271 #endif 272 273 #ifdef CONFIG_ATMEL_SPI 274 at91_spi0_hw_init(1 << 0); 275 at91_spi0_hw_init(1 << 4); 276 #endif 277 278 #ifdef CONFIG_MACB 279 at91_macb_hw_init(); 280 #endif 281 282 #ifdef CONFIG_LCD 283 at91sam9x5ek_lcd_hw_init(); 284 #endif 285 return 0; 286 } 287 288 int dram_init(void) 289 { 290 gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE, 291 CONFIG_SYS_SDRAM_SIZE); 292 return 0; 293 } 294