1 /* 2 * Copyright (C) 2012 Atmel Corporation 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <asm/io.h> 25 #include <asm/arch/at91sam9x5_matrix.h> 26 #include <asm/arch/at91sam9_smc.h> 27 #include <asm/arch/at91_common.h> 28 #include <asm/arch/at91_pmc.h> 29 #include <asm/arch/at91_rstc.h> 30 #include <asm/arch/gpio.h> 31 #include <asm/arch/clk.h> 32 #include <lcd.h> 33 #include <atmel_hlcdc.h> 34 #ifdef CONFIG_MACB 35 #include <net.h> 36 #endif 37 #include <netdev.h> 38 #ifdef CONFIG_LCD_INFO 39 #include <nand.h> 40 #include <version.h> 41 #endif 42 #ifdef CONFIG_ATMEL_SPI 43 #include <spi.h> 44 #endif 45 46 DECLARE_GLOBAL_DATA_PTR; 47 48 /* ------------------------------------------------------------------------- */ 49 /* 50 * Miscelaneous platform dependent initialisations 51 */ 52 #ifdef CONFIG_CMD_NAND 53 static void at91sam9x5ek_nand_hw_init(void) 54 { 55 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 56 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 57 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 58 unsigned long csa; 59 60 /* Enable CS3 */ 61 csa = readl(&matrix->ebicsa); 62 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; 63 /* NAND flash on D16 */ 64 csa |= AT91_MATRIX_NFD0_ON_D16; 65 66 /* Configure IO drive */ 67 csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL; 68 69 writel(csa, &matrix->ebicsa); 70 71 /* Configure SMC CS3 for NAND/SmartMedia */ 72 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | 73 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), 74 &smc->cs[3].setup); 75 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | 76 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6), 77 &smc->cs[3].pulse); 78 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6), 79 &smc->cs[3].cycle); 80 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 81 AT91_SMC_MODE_EXNW_DISABLE | 82 #ifdef CONFIG_SYS_NAND_DBW_16 83 AT91_SMC_MODE_DBW_16 | 84 #else /* CONFIG_SYS_NAND_DBW_8 */ 85 AT91_SMC_MODE_DBW_8 | 86 #endif 87 AT91_SMC_MODE_TDF_CYCLE(1), 88 &smc->cs[3].mode); 89 90 writel(1 << ATMEL_ID_PIOCD, &pmc->pcer); 91 92 /* Configure RDY/BSY */ 93 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); 94 /* Enable NandFlash */ 95 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 96 97 at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ 98 at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ 99 at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */ 100 at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */ 101 at91_set_a_periph(AT91_PIO_PORTD, 6, 1); 102 at91_set_a_periph(AT91_PIO_PORTD, 7, 1); 103 at91_set_a_periph(AT91_PIO_PORTD, 8, 1); 104 at91_set_a_periph(AT91_PIO_PORTD, 9, 1); 105 at91_set_a_periph(AT91_PIO_PORTD, 10, 1); 106 at91_set_a_periph(AT91_PIO_PORTD, 11, 1); 107 at91_set_a_periph(AT91_PIO_PORTD, 12, 1); 108 at91_set_a_periph(AT91_PIO_PORTD, 13, 1); 109 } 110 #endif 111 112 int board_eth_init(bd_t *bis) 113 { 114 int rc = 0; 115 116 #ifdef CONFIG_MACB 117 if (has_emac0()) 118 rc = macb_eth_initialize(0, 119 (void *)ATMEL_BASE_EMAC0, 0x00); 120 if (has_emac1()) 121 rc = macb_eth_initialize(1, 122 (void *)ATMEL_BASE_EMAC1, 0x00); 123 #endif 124 return rc; 125 } 126 127 #ifdef CONFIG_LCD 128 vidinfo_t panel_info = { 129 .vl_col = 800, 130 .vl_row = 480, 131 .vl_clk = 24000000, 132 .vl_sync = LCDC_LCDCFG5_HSPOL | LCDC_LCDCFG5_VSPOL, 133 .vl_bpix = LCD_BPP, 134 .vl_tft = 1, 135 .vl_clk_pol = 1, 136 .vl_hsync_len = 128, 137 .vl_left_margin = 64, 138 .vl_right_margin = 64, 139 .vl_vsync_len = 2, 140 .vl_upper_margin = 22, 141 .vl_lower_margin = 21, 142 .mmio = ATMEL_BASE_LCDC, 143 }; 144 145 void lcd_enable(void) 146 { 147 if (has_lcdc()) 148 at91_set_a_periph(AT91_PIO_PORTC, 29, 1); /* power up */ 149 } 150 151 void lcd_disable(void) 152 { 153 if (has_lcdc()) 154 at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* power down */ 155 } 156 157 static void at91sam9x5ek_lcd_hw_init(void) 158 { 159 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 160 161 if (has_lcdc()) { 162 at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDPWM */ 163 at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDVSYNC */ 164 at91_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDHSYNC */ 165 at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDISP */ 166 at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDEN */ 167 at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDPCK */ 168 169 at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDD0 */ 170 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDD1 */ 171 at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDD2 */ 172 at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDD3 */ 173 at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD4 */ 174 at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD5 */ 175 at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD6 */ 176 at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD7 */ 177 at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD8 */ 178 at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD9 */ 179 at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD10 */ 180 at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD11 */ 181 at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDD12 */ 182 at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD13 */ 183 at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD14 */ 184 at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD15 */ 185 at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD16 */ 186 at91_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDD17 */ 187 at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD18 */ 188 at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD19 */ 189 at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD20 */ 190 at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD21 */ 191 at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */ 192 at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */ 193 194 writel(1 << ATMEL_ID_LCDC, &pmc->pcer); 195 } 196 } 197 198 #ifdef CONFIG_LCD_INFO 199 void lcd_show_board_info(void) 200 { 201 ulong dram_size, nand_size; 202 int i; 203 char temp[32]; 204 205 if (has_lcdc()) { 206 lcd_printf("%s\n", U_BOOT_VERSION); 207 lcd_printf("(C) 2012 ATMEL Corp\n"); 208 lcd_printf("at91support@atmel.com\n"); 209 lcd_printf("%s CPU at %s MHz\n", 210 get_cpu_name(), 211 strmhz(temp, get_cpu_clk_rate())); 212 213 dram_size = 0; 214 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 215 dram_size += gd->bd->bi_dram[i].size; 216 nand_size = 0; 217 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 218 nand_size += nand_info[i].size; 219 lcd_printf(" %ld MB SDRAM, %ld MB NAND\n", 220 dram_size >> 20, 221 nand_size >> 20); 222 } 223 } 224 #endif /* CONFIG_LCD_INFO */ 225 #endif /* CONFIG_LCD */ 226 227 /* SPI chip select control */ 228 #ifdef CONFIG_ATMEL_SPI 229 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 230 { 231 return bus == 0 && cs < 2; 232 } 233 234 void spi_cs_activate(struct spi_slave *slave) 235 { 236 switch (slave->cs) { 237 case 1: 238 at91_set_pio_output(AT91_PIO_PORTA, 7, 0); 239 break; 240 case 0: 241 default: 242 at91_set_pio_output(AT91_PIO_PORTA, 14, 0); 243 break; 244 } 245 } 246 247 void spi_cs_deactivate(struct spi_slave *slave) 248 { 249 switch (slave->cs) { 250 case 1: 251 at91_set_pio_output(AT91_PIO_PORTA, 7, 1); 252 break; 253 case 0: 254 default: 255 at91_set_pio_output(AT91_PIO_PORTA, 14, 1); 256 break; 257 } 258 } 259 #endif /* CONFIG_ATMEL_SPI */ 260 261 int board_early_init_f(void) 262 { 263 at91_seriald_hw_init(); 264 return 0; 265 } 266 267 int board_init(void) 268 { 269 /* arch number of AT91SAM9X5EK-Board */ 270 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9X5EK; 271 272 /* adress of boot parameters */ 273 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 274 275 #ifdef CONFIG_CMD_NAND 276 at91sam9x5ek_nand_hw_init(); 277 #endif 278 279 #ifdef CONFIG_ATMEL_SPI 280 at91_spi0_hw_init(1 << 0); 281 at91_spi0_hw_init(1 << 4); 282 #endif 283 284 #ifdef CONFIG_MACB 285 at91_macb_hw_init(); 286 #endif 287 288 #ifdef CONFIG_LCD 289 at91sam9x5ek_lcd_hw_init(); 290 #endif 291 return 0; 292 } 293 294 int dram_init(void) 295 { 296 gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE, 297 CONFIG_SYS_SDRAM_SIZE); 298 return 0; 299 } 300