1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2007-2008
4  * Stelian Pop <stelian@popies.net>
5  * Lead Tech Design <www.leadtechdesign.com>
6  */
7 
8 #include <common.h>
9 #include <debug_uart.h>
10 #include <asm/io.h>
11 #include <asm/mach-types.h>
12 #include <asm/arch/at91sam9rl.h>
13 #include <asm/arch/at91sam9rl_matrix.h>
14 #include <asm/arch/at91sam9_smc.h>
15 #include <asm/arch/at91_common.h>
16 #include <asm/arch/at91_rstc.h>
17 #include <asm/arch/clk.h>
18 #include <asm/arch/gpio.h>
19 
20 #include <lcd.h>
21 #include <atmel_lcdc.h>
22 
23 DECLARE_GLOBAL_DATA_PTR;
24 
25 /* ------------------------------------------------------------------------- */
26 /*
27  * Miscelaneous platform dependent initialisations
28  */
29 
30 #ifdef CONFIG_CMD_NAND
31 static void at91sam9rlek_nand_hw_init(void)
32 {
33 	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
34 	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
35 	unsigned long csa;
36 
37 	/* Enable CS3 */
38 	csa = readl(&matrix->ebicsa);
39 	csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
40 
41 	writel(csa, &matrix->ebicsa);
42 
43 	/* Configure SMC CS3 for NAND/SmartMedia */
44 	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
45 		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
46 		&smc->cs[3].setup);
47 	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
48 		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
49 		&smc->cs[3].pulse);
50 	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
51 		&smc->cs[3].cycle);
52 	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
53 		AT91_SMC_MODE_EXNW_DISABLE |
54 #ifdef CONFIG_SYS_NAND_DBW_16
55 		AT91_SMC_MODE_DBW_16 |
56 #else /* CONFIG_SYS_NAND_DBW_8 */
57 		AT91_SMC_MODE_DBW_8 |
58 #endif
59 		AT91_SMC_MODE_TDF_CYCLE(2),
60 		&smc->cs[3].mode);
61 
62 	at91_periph_clk_enable(ATMEL_ID_PIOD);
63 
64 	/* Configure RDY/BSY */
65 	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
66 
67 	/* Enable NandFlash */
68 	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
69 
70 	at91_set_A_periph(AT91_PIN_PB4, 0);		/* NANDOE */
71 	at91_set_A_periph(AT91_PIN_PB5, 0);		/* NANDWE */
72 }
73 #endif
74 
75 #ifdef CONFIG_LCD
76 vidinfo_t panel_info = {
77 	.vl_col =		240,
78 	.vl_row =		320,
79 	.vl_clk =		4965000,
80 	.vl_sync =		ATMEL_LCDC_INVLINE_INVERTED |
81 				ATMEL_LCDC_INVFRAME_INVERTED,
82 	.vl_bpix =		3,
83 	.vl_tft =		1,
84 	.vl_hsync_len =		5,
85 	.vl_left_margin =	1,
86 	.vl_right_margin =	33,
87 	.vl_vsync_len =		1,
88 	.vl_upper_margin =	1,
89 	.vl_lower_margin =	0,
90 	.mmio =			ATMEL_BASE_LCDC,
91 };
92 
93 void lcd_enable(void)
94 {
95 	at91_set_gpio_value(AT91_PIN_PA30, 0);  /* power up */
96 }
97 
98 void lcd_disable(void)
99 {
100 	at91_set_gpio_value(AT91_PIN_PA30, 1);  /* power down */
101 }
102 static void at91sam9rlek_lcd_hw_init(void)
103 {
104 	at91_set_B_periph(AT91_PIN_PC1, 0);	/* LCDPWR */
105 	at91_set_A_periph(AT91_PIN_PC5, 0);	/* LCDHSYNC */
106 	at91_set_A_periph(AT91_PIN_PC6, 0);	/* LCDDOTCK */
107 	at91_set_A_periph(AT91_PIN_PC7, 0);	/* LCDDEN */
108 	at91_set_A_periph(AT91_PIN_PC3, 0);	/* LCDCC */
109 	at91_set_B_periph(AT91_PIN_PC9, 0);	/* LCDD3 */
110 	at91_set_B_periph(AT91_PIN_PC10, 0);	/* LCDD4 */
111 	at91_set_B_periph(AT91_PIN_PC11, 0);	/* LCDD5 */
112 	at91_set_B_periph(AT91_PIN_PC12, 0);	/* LCDD6 */
113 	at91_set_B_periph(AT91_PIN_PC13, 0);	/* LCDD7 */
114 	at91_set_B_periph(AT91_PIN_PC15, 0);	/* LCDD11 */
115 	at91_set_B_periph(AT91_PIN_PC16, 0);	/* LCDD12 */
116 	at91_set_B_periph(AT91_PIN_PC17, 0);	/* LCDD13 */
117 	at91_set_B_periph(AT91_PIN_PC18, 0);	/* LCDD14 */
118 	at91_set_B_periph(AT91_PIN_PC19, 0);	/* LCDD15 */
119 	at91_set_B_periph(AT91_PIN_PC20, 0);	/* LCDD18 */
120 	at91_set_B_periph(AT91_PIN_PC21, 0);	/* LCDD19 */
121 	at91_set_B_periph(AT91_PIN_PC22, 0);	/* LCDD20 */
122 	at91_set_B_periph(AT91_PIN_PC23, 0);	/* LCDD21 */
123 	at91_set_B_periph(AT91_PIN_PC24, 0);	/* LCDD22 */
124 	at91_set_B_periph(AT91_PIN_PC25, 0);	/* LCDD23 */
125 
126 	at91_periph_clk_enable(ATMEL_ID_LCDC);
127 }
128 
129 #ifdef CONFIG_LCD_INFO
130 #include <nand.h>
131 #include <version.h>
132 
133 void lcd_show_board_info(void)
134 {
135 	ulong dram_size, nand_size;
136 	int i;
137 	char temp[32];
138 
139 	lcd_printf ("%s\n", U_BOOT_VERSION);
140 	lcd_printf ("(C) 2008 ATMEL Corp\n");
141 	lcd_printf ("at91support@atmel.com\n");
142 	lcd_printf ("%s CPU at %s MHz\n",
143 		ATMEL_CPU_NAME,
144 		strmhz(temp, get_cpu_clk_rate()));
145 
146 	dram_size = 0;
147 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
148 		dram_size += gd->bd->bi_dram[i].size;
149 	nand_size = 0;
150 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
151 		nand_size += get_nand_dev_by_index(i)->size;
152 	lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
153 		dram_size >> 20,
154 		nand_size >> 20 );
155 }
156 #endif /* CONFIG_LCD_INFO */
157 #endif
158 
159 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
160 void board_debug_uart_init(void)
161 {
162 	at91_seriald_hw_init();
163 }
164 #endif
165 
166 #ifdef CONFIG_BOARD_EARLY_INIT_F
167 int board_early_init_f(void)
168 {
169 #ifdef CONFIG_DEBUG_UART
170 	debug_uart_init();
171 #endif
172 	return 0;
173 }
174 #endif
175 
176 int board_init(void)
177 {
178 	/* arch number of AT91SAM9RLEK-Board */
179 	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK;
180 	/* adress of boot parameters */
181 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
182 
183 #ifdef CONFIG_CMD_NAND
184 	at91sam9rlek_nand_hw_init();
185 #endif
186 #ifdef CONFIG_LCD
187 	at91sam9rlek_lcd_hw_init();
188 #endif
189 	return 0;
190 }
191 
192 int dram_init(void)
193 {
194 	gd->ram_size = get_ram_size(
195 		(void *)CONFIG_SYS_SDRAM_BASE,
196 		CONFIG_SYS_SDRAM_SIZE);
197 	return 0;
198 }
199