1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian@popies.net> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <debug_uart.h> 11 #include <asm/io.h> 12 #include <asm/mach-types.h> 13 #include <asm/arch/at91sam9rl.h> 14 #include <asm/arch/at91sam9rl_matrix.h> 15 #include <asm/arch/at91sam9_smc.h> 16 #include <asm/arch/at91_common.h> 17 #include <asm/arch/at91_rstc.h> 18 #include <asm/arch/clk.h> 19 #include <asm/arch/gpio.h> 20 21 #include <lcd.h> 22 #include <atmel_lcdc.h> 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 /* ------------------------------------------------------------------------- */ 27 /* 28 * Miscelaneous platform dependent initialisations 29 */ 30 31 #ifdef CONFIG_CMD_NAND 32 static void at91sam9rlek_nand_hw_init(void) 33 { 34 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 35 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 36 unsigned long csa; 37 38 /* Enable CS3 */ 39 csa = readl(&matrix->ebicsa); 40 csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; 41 42 writel(csa, &matrix->ebicsa); 43 44 /* Configure SMC CS3 for NAND/SmartMedia */ 45 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | 46 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), 47 &smc->cs[3].setup); 48 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | 49 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), 50 &smc->cs[3].pulse); 51 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), 52 &smc->cs[3].cycle); 53 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 54 AT91_SMC_MODE_EXNW_DISABLE | 55 #ifdef CONFIG_SYS_NAND_DBW_16 56 AT91_SMC_MODE_DBW_16 | 57 #else /* CONFIG_SYS_NAND_DBW_8 */ 58 AT91_SMC_MODE_DBW_8 | 59 #endif 60 AT91_SMC_MODE_TDF_CYCLE(2), 61 &smc->cs[3].mode); 62 63 at91_periph_clk_enable(ATMEL_ID_PIOD); 64 65 /* Configure RDY/BSY */ 66 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); 67 68 /* Enable NandFlash */ 69 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 70 71 at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */ 72 at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */ 73 } 74 #endif 75 76 #ifdef CONFIG_LCD 77 vidinfo_t panel_info = { 78 .vl_col = 240, 79 .vl_row = 320, 80 .vl_clk = 4965000, 81 .vl_sync = ATMEL_LCDC_INVLINE_INVERTED | 82 ATMEL_LCDC_INVFRAME_INVERTED, 83 .vl_bpix = 3, 84 .vl_tft = 1, 85 .vl_hsync_len = 5, 86 .vl_left_margin = 1, 87 .vl_right_margin = 33, 88 .vl_vsync_len = 1, 89 .vl_upper_margin = 1, 90 .vl_lower_margin = 0, 91 .mmio = ATMEL_BASE_LCDC, 92 }; 93 94 void lcd_enable(void) 95 { 96 at91_set_gpio_value(AT91_PIN_PA30, 0); /* power up */ 97 } 98 99 void lcd_disable(void) 100 { 101 at91_set_gpio_value(AT91_PIN_PA30, 1); /* power down */ 102 } 103 static void at91sam9rlek_lcd_hw_init(void) 104 { 105 at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */ 106 at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */ 107 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */ 108 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDDEN */ 109 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDCC */ 110 at91_set_B_periph(AT91_PIN_PC9, 0); /* LCDD3 */ 111 at91_set_B_periph(AT91_PIN_PC10, 0); /* LCDD4 */ 112 at91_set_B_periph(AT91_PIN_PC11, 0); /* LCDD5 */ 113 at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD6 */ 114 at91_set_B_periph(AT91_PIN_PC13, 0); /* LCDD7 */ 115 at91_set_B_periph(AT91_PIN_PC15, 0); /* LCDD11 */ 116 at91_set_B_periph(AT91_PIN_PC16, 0); /* LCDD12 */ 117 at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD13 */ 118 at91_set_B_periph(AT91_PIN_PC18, 0); /* LCDD14 */ 119 at91_set_B_periph(AT91_PIN_PC19, 0); /* LCDD15 */ 120 at91_set_B_periph(AT91_PIN_PC20, 0); /* LCDD18 */ 121 at91_set_B_periph(AT91_PIN_PC21, 0); /* LCDD19 */ 122 at91_set_B_periph(AT91_PIN_PC22, 0); /* LCDD20 */ 123 at91_set_B_periph(AT91_PIN_PC23, 0); /* LCDD21 */ 124 at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */ 125 at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */ 126 127 at91_periph_clk_enable(ATMEL_ID_LCDC); 128 } 129 130 #ifdef CONFIG_LCD_INFO 131 #include <nand.h> 132 #include <version.h> 133 134 void lcd_show_board_info(void) 135 { 136 ulong dram_size, nand_size; 137 int i; 138 char temp[32]; 139 140 lcd_printf ("%s\n", U_BOOT_VERSION); 141 lcd_printf ("(C) 2008 ATMEL Corp\n"); 142 lcd_printf ("at91support@atmel.com\n"); 143 lcd_printf ("%s CPU at %s MHz\n", 144 ATMEL_CPU_NAME, 145 strmhz(temp, get_cpu_clk_rate())); 146 147 dram_size = 0; 148 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 149 dram_size += gd->bd->bi_dram[i].size; 150 nand_size = 0; 151 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 152 nand_size += nand_info[i]->size; 153 lcd_printf (" %ld MB SDRAM, %ld MB NAND\n", 154 dram_size >> 20, 155 nand_size >> 20 ); 156 } 157 #endif /* CONFIG_LCD_INFO */ 158 #endif 159 160 #ifdef CONFIG_DEBUG_UART_BOARD_INIT 161 void board_debug_uart_init(void) 162 { 163 at91_seriald_hw_init(); 164 } 165 #endif 166 167 #ifdef CONFIG_BOARD_EARLY_INIT_F 168 int board_early_init_f(void) 169 { 170 #ifdef CONFIG_DEBUG_UART 171 debug_uart_init(); 172 #endif 173 return 0; 174 } 175 #endif 176 177 int board_init(void) 178 { 179 /* arch number of AT91SAM9RLEK-Board */ 180 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK; 181 /* adress of boot parameters */ 182 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 183 184 #ifdef CONFIG_CMD_NAND 185 at91sam9rlek_nand_hw_init(); 186 #endif 187 #ifdef CONFIG_HAS_DATAFLASH 188 at91_spi0_hw_init(1 << 0); 189 #endif 190 #ifdef CONFIG_LCD 191 at91sam9rlek_lcd_hw_init(); 192 #endif 193 return 0; 194 } 195 196 int dram_init(void) 197 { 198 gd->ram_size = get_ram_size( 199 (void *)CONFIG_SYS_SDRAM_BASE, 200 CONFIG_SYS_SDRAM_SIZE); 201 return 0; 202 } 203