1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian@popies.net> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/io.h> 11 #include <asm/arch/at91sam9rl.h> 12 #include <asm/arch/at91sam9rl_matrix.h> 13 #include <asm/arch/at91sam9_smc.h> 14 #include <asm/arch/at91_common.h> 15 #include <asm/arch/at91_pmc.h> 16 #include <asm/arch/at91_rstc.h> 17 #include <asm/arch/clk.h> 18 #include <asm/arch/gpio.h> 19 20 #include <lcd.h> 21 #include <atmel_lcdc.h> 22 #include <atmel_mci.h> 23 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) 24 #include <net.h> 25 #endif 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 /* ------------------------------------------------------------------------- */ 30 /* 31 * Miscelaneous platform dependent initialisations 32 */ 33 34 #ifdef CONFIG_CMD_NAND 35 static void at91sam9rlek_nand_hw_init(void) 36 { 37 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 38 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 39 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 40 unsigned long csa; 41 42 /* Enable CS3 */ 43 csa = readl(&matrix->ebicsa); 44 csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; 45 46 writel(csa, &matrix->ebicsa); 47 48 /* Configure SMC CS3 for NAND/SmartMedia */ 49 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | 50 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), 51 &smc->cs[3].setup); 52 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | 53 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), 54 &smc->cs[3].pulse); 55 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), 56 &smc->cs[3].cycle); 57 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 58 AT91_SMC_MODE_EXNW_DISABLE | 59 #ifdef CONFIG_SYS_NAND_DBW_16 60 AT91_SMC_MODE_DBW_16 | 61 #else /* CONFIG_SYS_NAND_DBW_8 */ 62 AT91_SMC_MODE_DBW_8 | 63 #endif 64 AT91_SMC_MODE_TDF_CYCLE(2), 65 &smc->cs[3].mode); 66 67 writel(1 << ATMEL_ID_PIOD, &pmc->pcer); 68 69 /* Configure RDY/BSY */ 70 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); 71 72 /* Enable NandFlash */ 73 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 74 75 at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */ 76 at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */ 77 } 78 #endif 79 80 #ifdef CONFIG_LCD 81 vidinfo_t panel_info = { 82 .vl_col = 240, 83 .vl_row = 320, 84 .vl_clk = 4965000, 85 .vl_sync = ATMEL_LCDC_INVLINE_INVERTED | 86 ATMEL_LCDC_INVFRAME_INVERTED, 87 .vl_bpix = 3, 88 .vl_tft = 1, 89 .vl_hsync_len = 5, 90 .vl_left_margin = 1, 91 .vl_right_margin = 33, 92 .vl_vsync_len = 1, 93 .vl_upper_margin = 1, 94 .vl_lower_margin = 0, 95 .mmio = ATMEL_BASE_LCDC, 96 }; 97 98 void lcd_enable(void) 99 { 100 at91_set_gpio_value(AT91_PIN_PA30, 0); /* power up */ 101 } 102 103 void lcd_disable(void) 104 { 105 at91_set_gpio_value(AT91_PIN_PA30, 1); /* power down */ 106 } 107 static void at91sam9rlek_lcd_hw_init(void) 108 { 109 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 110 111 at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */ 112 at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */ 113 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */ 114 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDDEN */ 115 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDCC */ 116 at91_set_B_periph(AT91_PIN_PC9, 0); /* LCDD3 */ 117 at91_set_B_periph(AT91_PIN_PC10, 0); /* LCDD4 */ 118 at91_set_B_periph(AT91_PIN_PC11, 0); /* LCDD5 */ 119 at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD6 */ 120 at91_set_B_periph(AT91_PIN_PC13, 0); /* LCDD7 */ 121 at91_set_B_periph(AT91_PIN_PC15, 0); /* LCDD11 */ 122 at91_set_B_periph(AT91_PIN_PC16, 0); /* LCDD12 */ 123 at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD13 */ 124 at91_set_B_periph(AT91_PIN_PC18, 0); /* LCDD14 */ 125 at91_set_B_periph(AT91_PIN_PC19, 0); /* LCDD15 */ 126 at91_set_B_periph(AT91_PIN_PC20, 0); /* LCDD18 */ 127 at91_set_B_periph(AT91_PIN_PC21, 0); /* LCDD19 */ 128 at91_set_B_periph(AT91_PIN_PC22, 0); /* LCDD20 */ 129 at91_set_B_periph(AT91_PIN_PC23, 0); /* LCDD21 */ 130 at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */ 131 at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */ 132 133 writel(1 << ATMEL_ID_LCDC, &pmc->pcer); 134 } 135 136 #ifdef CONFIG_LCD_INFO 137 #include <nand.h> 138 #include <version.h> 139 140 void lcd_show_board_info(void) 141 { 142 ulong dram_size, nand_size; 143 int i; 144 char temp[32]; 145 146 lcd_printf ("%s\n", U_BOOT_VERSION); 147 lcd_printf ("(C) 2008 ATMEL Corp\n"); 148 lcd_printf ("at91support@atmel.com\n"); 149 lcd_printf ("%s CPU at %s MHz\n", 150 ATMEL_CPU_NAME, 151 strmhz(temp, get_cpu_clk_rate())); 152 153 dram_size = 0; 154 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 155 dram_size += gd->bd->bi_dram[i].size; 156 nand_size = 0; 157 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 158 nand_size += nand_info[i].size; 159 lcd_printf (" %ld MB SDRAM, %ld MB NAND\n", 160 dram_size >> 20, 161 nand_size >> 20 ); 162 } 163 #endif /* CONFIG_LCD_INFO */ 164 #endif 165 166 #ifdef CONFIG_GENERIC_ATMEL_MCI 167 int board_mmc_init(bd_t *bis) 168 { 169 at91_mci_hw_init(); 170 171 return atmel_mci_init((void *)ATMEL_BASE_MCI); 172 } 173 #endif 174 175 int board_early_init_f(void) 176 { 177 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 178 179 /* Enable clocks for all PIOs */ 180 writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) | 181 (1 << ATMEL_ID_PIOC) | (1 << ATMEL_ID_PIOD), 182 &pmc->pcer); 183 184 return 0; 185 } 186 187 int board_init(void) 188 { 189 /* arch number of AT91SAM9RLEK-Board */ 190 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK; 191 /* adress of boot parameters */ 192 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 193 194 at91_seriald_hw_init(); 195 #ifdef CONFIG_CMD_NAND 196 at91sam9rlek_nand_hw_init(); 197 #endif 198 #ifdef CONFIG_HAS_DATAFLASH 199 at91_spi0_hw_init(1 << 0); 200 #endif 201 #ifdef CONFIG_LCD 202 at91sam9rlek_lcd_hw_init(); 203 #endif 204 return 0; 205 } 206 207 int dram_init(void) 208 { 209 gd->ram_size = get_ram_size( 210 (void *)CONFIG_SYS_SDRAM_BASE, 211 CONFIG_SYS_SDRAM_SIZE); 212 return 0; 213 } 214