1 /* 2 * (C) Copyright 2013 Atmel Corporation 3 * Josh Wu <josh.wu@atmel.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <asm/io.h> 26 #include <asm/arch/at91sam9x5_matrix.h> 27 #include <asm/arch/at91sam9_smc.h> 28 #include <asm/arch/at91_common.h> 29 #include <asm/arch/at91_pmc.h> 30 #include <asm/arch/at91_rstc.h> 31 #include <asm/arch/at91_pio.h> 32 #include <asm/arch/clk.h> 33 #include <lcd.h> 34 #include <atmel_hlcdc.h> 35 #include <atmel_mci.h> 36 #include <netdev.h> 37 38 #ifdef CONFIG_LCD_INFO 39 #include <nand.h> 40 #include <version.h> 41 #endif 42 43 DECLARE_GLOBAL_DATA_PTR; 44 45 /* ------------------------------------------------------------------------- */ 46 /* 47 * Miscelaneous platform dependent initialisations 48 */ 49 #ifdef CONFIG_NAND_ATMEL 50 static void at91sam9n12ek_nand_hw_init(void) 51 { 52 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 53 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 54 unsigned long csa; 55 56 /* Assign CS3 to NAND/SmartMedia Interface */ 57 csa = readl(&matrix->ebicsa); 58 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; 59 /* Configure databus */ 60 csa &= ~AT91_MATRIX_NFD0_ON_D16; /* nandflash connect to D0~D15 */ 61 /* Configure IO drive */ 62 csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL; 63 64 writel(csa, &matrix->ebicsa); 65 66 /* Configure SMC CS3 for NAND/SmartMedia */ 67 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | 68 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), 69 &smc->cs[3].setup); 70 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | 71 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6), 72 &smc->cs[3].pulse); 73 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(7), 74 &smc->cs[3].cycle); 75 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 76 AT91_SMC_MODE_EXNW_DISABLE | 77 #ifdef CONFIG_SYS_NAND_DBW_16 78 AT91_SMC_MODE_DBW_16 | 79 #else /* CONFIG_SYS_NAND_DBW_8 */ 80 AT91_SMC_MODE_DBW_8 | 81 #endif 82 AT91_SMC_MODE_TDF_CYCLE(1), 83 &smc->cs[3].mode); 84 85 /* Configure RDY/BSY pin */ 86 at91_set_pio_input(AT91_PIO_PORTD, 5, 1); 87 88 /* Configure ENABLE pin for NandFlash */ 89 at91_set_pio_output(AT91_PIO_PORTD, 4, 1); 90 91 at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ 92 at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ 93 at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* ALE */ 94 at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* CLE */ 95 } 96 #endif 97 98 #ifdef CONFIG_LCD 99 vidinfo_t panel_info = { 100 .vl_col = 480, 101 .vl_row = 272, 102 .vl_clk = 9000000, 103 .vl_bpix = LCD_BPP, 104 .vl_sync = 0, 105 .vl_tft = 1, 106 .vl_hsync_len = 5, 107 .vl_left_margin = 8, 108 .vl_right_margin = 43, 109 .vl_vsync_len = 10, 110 .vl_upper_margin = 4, 111 .vl_lower_margin = 12, 112 .mmio = ATMEL_BASE_LCDC, 113 }; 114 115 void lcd_enable(void) 116 { 117 at91_set_pio_output(AT91_PIO_PORTC, 25, 0); /* power up */ 118 } 119 120 void lcd_disable(void) 121 { 122 at91_set_pio_output(AT91_PIO_PORTC, 25, 1); /* power down */ 123 } 124 125 #ifdef CONFIG_LCD_INFO 126 void lcd_show_board_info(void) 127 { 128 ulong dram_size, nand_size; 129 int i; 130 char temp[32]; 131 132 lcd_printf("%s\n", U_BOOT_VERSION); 133 lcd_printf("ATMEL Corp\n"); 134 lcd_printf("at91@atmel.com\n"); 135 lcd_printf("%s CPU at %s MHz\n", 136 ATMEL_CPU_NAME, 137 strmhz(temp, get_cpu_clk_rate())); 138 139 dram_size = 0; 140 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 141 dram_size += gd->bd->bi_dram[i].size; 142 nand_size = 0; 143 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 144 nand_size += nand_info[i].size; 145 lcd_printf(" %ld MB SDRAM, %ld MB NAND\n", 146 dram_size >> 20, 147 nand_size >> 20); 148 } 149 #endif /* CONFIG_LCD_INFO */ 150 #endif /* CONFIG_LCD */ 151 152 /* SPI chip select control */ 153 #ifdef CONFIG_ATMEL_SPI 154 #include <spi.h> 155 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 156 { 157 return bus == 0 && cs < 2; 158 } 159 160 void spi_cs_activate(struct spi_slave *slave) 161 { 162 switch (slave->cs) { 163 case 0: 164 at91_set_pio_output(AT91_PIO_PORTA, 14, 0); 165 break; 166 case 1: 167 at91_set_pio_output(AT91_PIO_PORTA, 7, 0); 168 break; 169 } 170 } 171 172 void spi_cs_deactivate(struct spi_slave *slave) 173 { 174 switch (slave->cs) { 175 case 0: 176 at91_set_pio_output(AT91_PIO_PORTA, 14, 1); 177 break; 178 case 1: 179 at91_set_pio_output(AT91_PIO_PORTA, 7, 1); 180 break; 181 } 182 } 183 #endif /* CONFIG_ATMEL_SPI */ 184 185 #ifdef CONFIG_GENERIC_ATMEL_MCI 186 int board_mmc_init(bd_t *bd) 187 { 188 at91_mci_hw_init(); 189 190 return atmel_mci_init((void *)ATMEL_BASE_HSMCI0); 191 } 192 #endif 193 194 #ifdef CONFIG_KS8851_MLL 195 void at91sam9n12ek_ks8851_hw_init(void) 196 { 197 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 198 199 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | 200 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), 201 &smc->cs[2].setup); 202 writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) | 203 AT91_SMC_PULSE_NRD(7) | AT91_SMC_PULSE_NCS_RD(7), 204 &smc->cs[2].pulse); 205 writel(AT91_SMC_CYCLE_NWE(9) | AT91_SMC_CYCLE_NRD(9), 206 &smc->cs[2].cycle); 207 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 208 AT91_SMC_MODE_EXNW_DISABLE | 209 AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 | 210 AT91_SMC_MODE_TDF_CYCLE(1), 211 &smc->cs[2].mode); 212 213 /* Configure NCS2 PIN */ 214 at91_set_b_periph(AT91_PIO_PORTD, 19, 0); 215 } 216 #endif 217 218 int board_early_init_f(void) 219 { 220 /* Enable clocks for all PIOs */ 221 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 222 writel((1 << ATMEL_ID_PIOAB) | (1 << ATMEL_ID_PIOCD), &pmc->pcer); 223 224 at91_seriald_hw_init(); 225 return 0; 226 } 227 228 int board_init(void) 229 { 230 /* adress of boot parameters */ 231 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 232 233 #ifdef CONFIG_NAND_ATMEL 234 at91sam9n12ek_nand_hw_init(); 235 #endif 236 237 #ifdef CONFIG_ATMEL_SPI 238 at91_spi0_hw_init(1 << 0); 239 #endif 240 241 #ifdef CONFIG_LCD 242 at91_lcd_hw_init(); 243 #endif 244 245 #ifdef CONFIG_KS8851_MLL 246 at91sam9n12ek_ks8851_hw_init(); 247 #endif 248 249 return 0; 250 } 251 252 #ifdef CONFIG_KS8851_MLL 253 int board_eth_init(bd_t *bis) 254 { 255 return ks8851_mll_initialize(0, CONFIG_KS8851_MLL_BASEADDR); 256 } 257 #endif 258 259 int dram_init(void) 260 { 261 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 262 CONFIG_SYS_SDRAM_SIZE); 263 return 0; 264 } 265